78M6610+PSU/EK#1 Maxim Integrated, 78M6610+PSU/EK#1 Datasheet - Page 51

• Manufacturer Part Number: 78M6610+PSU/EK#1
• Description: Development Boards & Kits - Other Processors 78M6610 EVAL KIT
• Manufacturer: Maxim Integrated

Specifications of 78M6610+PSU/EK#1

• Rohs: yes
• Part # Aliases: 90-X6610#KK1

for write) are clocked onto the bus by the master. This indicates to the addressed slave receiver that the
register address will follow after it has generated an acknowledge bit (A) during the ninth clock cycle.
Therefore, the next byte transmitted by the master is the register address and will be written into the
address pointer of the 78M6610+PSU. After receiving another acknowledge (A) signal from the
write cycle. The example in
Upon receiving a STOP (P) condition, the internal register address pointer will be incremented.
The write access can be extended to multiple sequential registers.
previous read access was to register address n, the next current address read operation would access
data from address n + 1.
Upon receipt of the control byte with R/W bit set to one, the 78M6610+PSU issues an acknowledge (A)
and transmits the eight bit data byte. The master will not acknowledge the transfer, but generates a STOP
condition to end the transfer and the 78M6610+PSU will discontinue the transmission.
Write Operations
Following the START (S) condition from the master, the device address (7-bits) and the R/W bit (logic low
78M6610+PSU the master device will transmit the data byte(s) to be written into the addressed memory
location. The data transfer ends when the master generates a stop (P) condition. This initiates the internal
multiple register are written sequentially.
Read Operations
Read operations are initiated in the same way as write operations with the exception that the R/W bit of
the control byte is set to one. There are two basic types of read operations: current address read and
random read.
Current Address Read: the 78M6610+PSU contains an address counter that maintains the address of the
last register accessed, internally incremented by one when the stop bit is received. Therefore, if the
This read operation is not limited to 3 bytes but can be extended until the register address pointer
reaches its maximum value.
Rev 1
S
S
T
A
R
T
S
S
T
A
R
T
S
S
T
A
R
T
0
0
Device Address
0
1
Device Address
Device Address
1
2
1
3
2
4
2
3
5
3
4
6
0
5
4
A
C
K
6
0
5
Register Address (n)
0
1
6
2
A
C
K
3
1
0
4
5
A
C
K
Figure 21: I
1
Register Address
6 7
2
0
Figure 20
A
C
K
3
1 2 3 4 5 6 7
0
4
1 2 3 4 5 6 7
5
Figure 20: I
6 7
Data
Data
2
shows a 3-byte data write (24-bit register write).
C Bus Multiple Sequential Register Write
A
C
K
0
A
C
K
1 2 3 4 5 6 7
0
REGISTER (n)
2
1 2 3 4 5 6 7
C Bus 3-byte Data Write
A
C
K
Data
Data
0
1 2 3 4 5 6 7
A
C
K
0
A
C
K
Data
1 2 3 4 5 6 7
0
1 2 3 4 5 6 7
Data
Data
Figure 21
A
C
K
A
C
K
0
1
0
REGISTER (n+1)
2 3 4
1 2 3 4 5 6 7
A
C
K
78M6610+PSU Data Sheet
shows a transaction where
0
Data
1 2 3 4 5 6 7
6 7
A
C
K
Data
REGISTER (n+2)
0
1
2 3 4
N
O
A
C
K
REGISTER (n+x)
P
A
C
K
S
T
O
P
6 7
P
S
T
O
P
A
C
K
P
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