78M6610+PSU/EK#1 Maxim Integrated, 78M6610+PSU/EK#1 Datasheet - Page 39

• Manufacturer Part Number: 78M6610+PSU/EK#1
• Description: Development Boards & Kits - Other Processors 78M6610 EVAL KIT
• Manufacturer: Maxim Integrated

Specifications of 78M6610+PSU/EK#1

• Rohs: yes
• Part # Aliases: 90-X6610#KK1

must divide the documented register address by 3. While access to a single byte is possible with some
interfaces, it is highly recommended that the user access words (or multiple words) of data with each
transaction.
time the status of these pins must not change.
the new address.
4 Serial Interfaces
All user registers are contained in a 256 word (24-bits each) area of the on-chip RAM and can be
accessed through the UART, SPI, or I
Serial Interface Selection
The 78M6610+PSU provides UART, I
at a time. The user activates the interface through the configuration of pins IFCONFIG and SSB/DIR/SCL
according to the following table.
The interface selection pins are sampled following power-on and reset. The user should allow at least 10
ms from a power-on or reset event for them to be latched and the serial interface selected. During this
Device Address (UART)
The UART interface supports a multi-point communications protocol. Each device is identified by a
specific address that is configured through the DevAddr register and pins Addr0 and Addr1 according to
the following figure. DevAddr Register Bits 23 through 7 are not used and should be set to 0. Their status
has no effect on the device address.
A change of the address is always effective after a power-on or reset. During the initialization following a
power-on or reset, the DevAddr register value is restored with the value contained in Flash memory and
the address pin status is acquired.
It is possible to modify the device address by setting the DevAddr register (through any of the interfaces)
as well as the address pins status. If DevAddr register is modified, it is necessary to save its content into
Flash through the ACC command. Following a reset or power-on the device will resume operation with
Rev 1
DevAddr Register bit 5:0
Warning
Where applicable, pins should be configured via pull-up and pull-down resistors as these pins
could become outputs after initialization. Therefore, direct connection to GNDD/GNDA or
V
3P3D
SPCK/ADDR0 Pin
/V
3P3A
ADDR1 Pin
supplies must be avoided.
Device Address (24-pin Package)
7 6
Selected Interface
SPI
UART
I
2
C
5
4
3
2
2
C, and SPI interface options, but only one interface can be active
C interfaces. For word-addressable SPI and I
2
1
0
SSB/DIR/SCL
X (don’t care)
0
1
DevAddr Register bit 6:0
SPCK/ADDR0 Pin
IFCONFIG
0
1
1
Device Address (16-pin Package)
78M6610+PSU Data Sheet
7 6
2
5
C interfaces, one
4
3
2
1
0
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