78M6610+PSU/EK#1 Maxim Integrated, 78M6610+PSU/EK#1 Datasheet - Page 47

• Manufacturer Part Number: 78M6610+PSU/EK#1
• Description: Development Boards & Kits - Other Processors 78M6610 EVAL KIT
• Manufacturer: Maxim Integrated

Specifications of 78M6610+PSU/EK#1

• Rohs: yes
• Part # Aliases: 90-X6610#KK1

The following are some transaction examples.
Example 1: Write access of address 0x14.
The second type of transaction is dedicated to transporting data between the host and the device and is
structured as follows:
Example 2: Read access of address 0x17 and 0x18.
Rev 1
Number
Byte
1
2
3
4
5
6
7
8
R/W: Defines the directionality of the transaction (Read = 0; Write = 1);
ADDR[5:0]: Indicates the remainder of the address to access.
(NbrAcc*3)+1
Number
(NbrAcc*3)+2
(NbrAcc*3)+3
(NbrAcc *3)
Byte
Number
1
2
3
4
5
Bit 7
Byte
…
1
2
3
4
5
6
7
Bit 7
NbrAcc[3:0] = 0x01
Bit 6
NbrAcc[3:0] = 0x00
Bit 7
Bit 6
Bit 6
Bit 5
Addr[5:0] = 0x17
Bit 5
Addr[5:0] = 0x14
Bit 5
ADDR[5:0]
Data[23:16] @ 0x14
Data[23:16] @ 0x17
Data[23:16] @ 0x18
DATA[23:16] @ Addr
DATA[15:8]
DATA[7:0]
DATA[23:16]
DATA[15:8] @ Addr +1
DATA[7:0] @ Addr +1
DATA[7:0] @ Addr + NbrAcc
DATA[23:16] @ Addr + NbrAcc
DATA[15:8] + NbrAcc
DATA[7:0] + NbrAcc
Bit 4
Data[15:8] @ 0x14
Data[15:8] @ 0x17
Data[15:8] @ 0x18
Bit 4
Data[7:0] @ 0x14
Data[7:0] @ 0x17
Data[7:0] @ 0x18
Bit 4
Addr7=0
Addr7=0
Bit 3
Bit 3
Bit 3
…
@ Addr
@ Addr
@ Addr + 1
Bit 2
Addr6=0
Addr6=0
Bit 2
Bit 2
Bit 1
R/W
78M6610+PSU Data Sheet
WR=1
Bit 1
0
RD=0
Bit 1
Bit 0
0
0
Bit 0
1
0
Bit 0
1
0
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