78M6610+PSU/EK#1 Maxim Integrated, 78M6610+PSU/EK#1 Datasheet - Page 48

• Manufacturer Part Number: 78M6610+PSU/EK#1
• Description: Development Boards & Kits - Other Processors 78M6610 EVAL KIT
• Manufacturer: Maxim Integrated

Specifications of 78M6610+PSU/EK#1

• Rohs: yes
• Part # Aliases: 90-X6610#KK1

during the “in-between-bytes” gap, as illustrated by Figure 18. Note that the figure shows two gaps, one
between the configuration and the data transactions and another between bytes within the data
transaction. The placement of those gaps is strictly for the purpose of illustrating the concept.
78M6610+PSU Data Sheet
Example 3: Non-Contiguous Read accesses of address 0x17 and 0x0A.
The timing of the transaction can be organized in different ways depending on the host capabilities. The
above transaction can be a succession of bytes as shown in Figure 17. Those bytes are carried by a
continuously active SCK, with eight clock periods per byte.
The host also has the possibility to space out the bytes transmitted. In such a case, SCK is inactive
48
SDO
SCK
SSB
SDI
SDO
SCK
SSB
SDI
Byte 1: Control
Byte#
SCK Active
10
1
2
3
4
5
6
7
8
9
Byte 1: Control
Bit 7
NbrAcc[3:0] = 0x00
NbrAcc[3:0] = 0x00
Bit 6
Figure 18: Write Access with Interrupted SCK
Byte 2: Addr & Ctrl
Byte 2: Addr & Ctrl
Figure 17: Write Access Example
Bit 5
Addr[5:0] = 0x17
Addr[5:0] = 0x0A
Bit 4
HiZ
Data[23:16] @ 0x0A
Data[23:16] @ 0x17
Data[15:8] @ 0x0A
Data[15:8] @ 0x17
Data[7:0] @ 0x17
Data[7:0] @ 0x0A
Byte 3: Data[23:16]
Byte 3: Data[23:16]
SCK Active
Addr7=0
Addr7=0
HiZ
Bit 3
SCK Active
Addr6=0
Addr6=0
Byte 4: Data[15:8]
Byte 4: Data[15:8]
Bit 2
RD=0
Bit 1
W=1
0
0
Byte 5: Data[7:0]
Bit 0
Byte 5: Data[7:0]
1
0
1
0
SCK Active
Rev 1