78M6610+PSU/EK#1 Maxim Integrated, 78M6610+PSU/EK#1 Datasheet - Page 41

• Manufacturer Part Number: 78M6610+PSU/EK#1
• Description: Development Boards & Kits - Other Processors 78M6610 EVAL KIT
• Manufacturer: Maxim Integrated

Specifications of 78M6610+PSU/EK#1

• Rohs: yes
• Part # Aliases: 90-X6610#KK1

•
The implemented SSI protocol uses binary packets, which contain synchronization, addressing, payload,
and data integrity check. The responses also contain acknowledge/error indicators.
The SSI ID for each 78M6610+PSU is defined by a device address that is configured through the register
DevAddr, which provides address bits 7 through 2 of the device address. While address bits 0 and 1 are
configured through pins ADDR1 and SPCK/ADDR0 (24-pin package). In 16-pin package devices, the
DevAddr register provides address bits 7 though 1, while bit 0 is configured through the pin
SPCK/ADDR0.
4.1 UART Interface
The byte-addressable UART interface on the 78M6610+PSU features a binary communication protocol
called SSI with two modes:
•
The supported configuration is 38400 baud, 8-bit, no-parity, 1 stop-bit, no flow control. The SSB/DIR/SCL
pin is used to drive an RS-485 transceiver output enable or direction pin.
Rev 1
A Command Response mode supporting single and multi-point communications, including direction
control for an RS-485 transceiver. This mode supports a 4-wire RS-485 bus.
An Auto Report mode that transmits data automatically at the completion of an accumulation interval
without host intervention.
78M6610+PSU
SDI/RX/SDAo
SDO/TX/SDAi
SSB/DIR/SCL
Figure 15: UART Connections on a RS-485 Bus
4.7K
ROUT
REN
DEN
DIN
78M6610+PSU Data Sheet
A
B
A
B
RS-485 BUS
RS-485 BUS
41