78M6610+PSU/EK#1 Maxim Integrated, 78M6610+PSU/EK#1 Datasheet - Page 49

• Manufacturer Part Number: 78M6610+PSU/EK#1
• Description: Development Boards & Kits - Other Processors 78M6610 EVAL KIT
• Manufacturer: Maxim Integrated

Specifications of 78M6610+PSU/EK#1

• Rohs: yes
• Part # Aliases: 90-X6610#KK1

The I
4.3 I
The 78M6610+PSU has an I
supports I
two possible configurations. Configuration A is the standard configuration. The double pin for SDA allows
the isolated configuration B.
on-chip RAM. The address of each register specified in Section 3 must be divided by 3 to obtain the
relevant address for the I
that the user access words (or multiple words) of data with each transaction.
The device address of each 78M6610+PSU is configured through the register DevAddr, which defines
address bits 6 through 2 of the device address. Address bits 0 and 1 are configured through pins ADDR1
and SPCK/ADDR0 (24-pin package). With the 16-pin package option, the DevAddr register defines
address bits 6 though 1, while bit 0 is configured through the pin SPCK/ADDR0.
Rev 1
SDAo
SDAi
SCK
2
C interface allows access to read and write registers contained in a 256 word (24-bit) area of the
A) STANDARD CONFIGURATION
2
C Interface
2
C slave mode with a 7-bit address and operates at a data rate up to 400 kHz. Figure 19 shows
Figure 19: I
V
3P3
2
C Bus Connection in Standard (A) and Isolated (B) Configuration
2
or 5VDC
C access. While access to a single byte is possible, it is highly recommended
V
3P3
2
C interface available at the SDAI, SDAO, and SCL pins. The interface
or 5VDC
SDA
SCK
SDAo
SDAi
SCK
B) ISOLATED CONFIGURATION
V
3P3
or 5VDC
78M6610+PSU Data Sheet
5VDC
5VDC
I2C_GND
SCK
SDA
49