IS46TR16128A-15HBLA2 ISSI, IS46TR16128A-15HBLA2 Datasheet - Page 66

• Manufacturer Part Number: IS46TR16128A-15HBLA2
• Description: DRAM 2G, 1.5v, 1333MT/s 128Mx16 DDR3
• Manufacturer: ISSI

Specifications of IS46TR16128A-15HBLA2

• Rohs: yes
• Data Bus Width: 16 bit
• Organization: 128 M x 16
• Package / Case: FBGA-96
• Memory Size: 2 Gbit
• Maximum Clock Frequency: 933 MHz
• Access Time: 13.125 ns
• Supply Voltage - Max: 1.575 V
• Supply Voltage - Min: 1.425 V
• Maximum Operating Current: 65 mA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT

IS43/46TR16128A, IS43/46TR16128AL,
IS43/46TR82560A, IS43/46TR82560AL
Delay from start of internal write transaction to
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00A
11/14/2012
DQS, DQS# differential input high pulse width
ACTIVE to ACTIVE command period for 1KB
ACTIVE to ACTIVE command period for 2KB
DQS, DQS# differential input low pulse width
Data hold time from DQS, DQS# referenced
DQ and DM Input pulse width for each input
DQS, DQS# falling edge hold time from CK,
DQS, DQS# rising edge output access time
ACTIVE to PRECHARGE command period
Command and Address hold time from CK,
Internal READ Command to PRECHARGE
Mode Register Set command update delay
Auto precharge write recovery + precharge
DQS, DQS# differential WRITE Postamble
DQS, DQS# falling edge setup time to CK,
DQS, DQS# rising edge to CK, CK# rising
DQS, DQS# differential READ Postamble
DQS, DQS# differential WRITE Preamble
Command and Address setup time to CK,
Command and Address setup time to CK,
CK# referenced to Vih(ac) / Vil(ac) levels
CK# referenced to Vih(dc) / Vil(dc) levels
CK# referenced to Vih(ac) / Vil(ac) levels
DQS,DQS# differential READ Preamble
DQS, DQS# differential output high time
Mode Register Set command cycle time
Four activate window for 1KB page size
Four activate window for 2KB page size
DQS, DQS# differential output low time
ACT to internal read or write delay time
Multi-Purpose Register Recovery Time
DQS and DQS# high-impedance time
ACT to ACT or REF command period
DQS and DQS# low-impedance time
CAS# to CAS# command delay
Command and Address Timing
(Referenced from RL + BL/2)
(Referenced from RL - 1)
to Vih(dc) / Vil(dc) levels
internal read command
PRE command period
WRITE recovery time
from rising CK, CK#
Data Strobe Timing
DLL locking time
Command delay
CK# rising edge
CK# rising edge
Parameter
page size
page size
edge
time
tDH(base)
tHZ(DQS)
tDAL(min)
tLZ(DQS)
tIH(base)
tIS(base)
tIS(base)
tDQSCK
Symbol
tWPRE
tWPST
tDQSH
tMPRR
DC100
tRPRE
tDQSL
tDQSS
AC150
tDIPW
tRPST
tDLLK
tMOD
tQSH
tWTR
tMRD
tRCD
tCCD
tRRD
tRRD
tFAW
tFAW
tDSS
tDSH
tRAS
tQSL
tRTP
tWR
tRP
tRC
max(4nCK,
ADD/CMD setup and
DDR3/DDR3L-1866
Min.
-0.27
-195
-390
0.45
0.45
0.18
0.18
6ns)
320
512
0.9
0.3
0.4
0.4
0.9
0.3
15
27
35
4
4
1
See table for
-
WR + roundup(tRP / tCK(avg))
tMODmin.: max(12nCK, 15ns)
tWTRmin.: max(4nCK, 7.5ns)
tRRDmin.: max(4nCK, 7.5ns)
tRTPmin.: max(4nCK, 7.5ns)
hold
Standard Speed Bins
Standard Speed Bins
Standard Speed Bins
Standard Speed Bins
Note 19
Note 11
Max.
0.55
0.55
0.27
195
195
195
tRTPmax.: -
tMODmax.:
-
-
-
-
-
-
-
-
tWTRmax.:
-
-
-
-
-
tRRDmax.:
-
-
max(4nCK,
DDR3/DDR3L-1866
Min.
6ns)
Max.
-
-
-
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
Units
Note
Note
nCK
nCK
nCK
nCK
nCK
ps
ps
ns
ns
ns
ps
ps
ps
66
13,19,g
11,13,g
b,16,27
13,14,f
13,14,f
Notes
29,31
30,31
d,17
13,g
13,g
c,32
c,32
e,18
b,16
b,16
13,f
28
22
c
e
e
e