IS46TR16128A-15HBLA2 ISSI, IS46TR16128A-15HBLA2 Datasheet - Page 34

• Manufacturer Part Number: IS46TR16128A-15HBLA2
• Description: DRAM 2G, 1.5v, 1333MT/s 128Mx16 DDR3
• Manufacturer: ISSI

Specifications of IS46TR16128A-15HBLA2

• Rohs: yes
• Data Bus Width: 16 bit
• Organization: 128 M x 16
• Package / Case: FBGA-96
• Memory Size: 2 Gbit
• Maximum Clock Frequency: 933 MHz
• Access Time: 13.125 ns
• Supply Voltage - Max: 1.575 V
• Supply Voltage - Min: 1.425 V
• Maximum Operating Current: 65 mA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT

IS43/46TR16128A, IS43/46TR16128AL,
IS43/46TR82560A, IS43/46TR82560AL
4.3. AC and DC Logic Input Levels for Differential Signals
4.3.1 Differential signal definition
4.3.2 Differential swing requirements for clock (CK - CK#) and strobe (DQS - DQS#)
Notes:
1. Used to define a differential signal slew-rate.
2. For CK - CK# use VIH/VIL(ac) of ADD/CMD and VREFCA; for DQS - DQS#, DQSL, DQSL#, DQSU, DQSU# use VIH/VIL(ac) of DQs and VREFDQ; if
3.
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00A
11/14/2012
VIHdiff(ac)
VIHdiff(ac)
VILdiff(ac)
VILdiff(ac)
a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here.
These values are not defined; however, the single-ended signals CK, CK#, DQS, DQS#, DQSL, DQSL#, DQSU, DQSU# need to be within the
respective limits (VIH(dc) max, VIL(dc)min) for single-ended signals as well as the limitations for overshoot and undershoot
Symbol
Symbol
VIHdiff
VIHdiff
VILdiff
VILdiff
4.3.2.1 Differential AC and DC Input Levels
Differential input logic high
Differential input logic high
Differential input logic low
Differential input logic low
Differential input high ac
Differential input high ac
Differential input low ac
Differential input low ac
Parameter
Parameter
Figure 4.3.1 Definition of differential ac-swing and “time above ac-level”
V
V
V
V
IH.DIFF.AC.MIN
IH.DIFF.MIN
IH.DIFF.MAX
IH.DIFF.AC.MAX
2 x ( VIH(ac) – Vref )
2 x ( VIH(ac) – Vref )
Half cycle
+0.200
+0.180
Note3
Note3
Note3
Note3
tDVAC
DDR3L-800, 1066, 1333, & 1600
Min
Min
DDR3-800, 1066, 1333, & 1600
tDVAC
2 x ( Vref - VIL(ac) )
2 x ( Vref - VIL(ac) )
-0.200
-0.180
Note3
Note3
Note3
Note3
Max
Max
time
.
unit
unit
V
V
V
V
V
V
V
V
34
Notes
Notes
1
1
2
2
1
1
2
2