IS46TR16128A-15HBLA2 ISSI, IS46TR16128A-15HBLA2 Datasheet - Page 63

• Manufacturer Part Number: IS46TR16128A-15HBLA2
• Description: DRAM 2G, 1.5v, 1333MT/s 128Mx16 DDR3
• Manufacturer: ISSI

Specifications of IS46TR16128A-15HBLA2

• Rohs: yes
• Data Bus Width: 16 bit
• Organization: 128 M x 16
• Package / Case: FBGA-96
• Memory Size: 2 Gbit
• Maximum Clock Frequency: 933 MHz
• Access Time: 13.125 ns
• Supply Voltage - Max: 1.575 V
• Supply Voltage - Min: 1.425 V
• Maximum Operating Current: 65 mA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT

IS43/46TR16128A, IS43/46TR16128AL,
IS43/46TR82560A, IS43/46TR82560AL
Delay from start of internal write transaction to
Exit Self Refresh to commands not requiring a
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00A
11/14/2012
DQS, DQS# differential input high pulse width
ACTIVE to ACTIVE command period for 1KB
ACTIVE to ACTIVE command period for 2KB
DQS, DQS# differential input low pulse width
DQS, DQS# falling edge hold time from CK,
ACTIVE to PRECHARGE command period
Command and Address hold time from CK,
Internal READ Command to PRECHARGE
Mode Register Set command update delay
Auto precharge write recovery + precharge
DQS, DQS# falling edge setup time to CK,
DQS, DQS# rising edge to CK, CK# rising
Command and Address setup time to CK,
Command and Address setup time to CK,
Control and Address Input pulse width for
CK# referenced to Vih(ac) / Vil(ac) levels
CK# referenced to Vih(dc) / Vil(dc) levels
CK# referenced to Vih(ac) / Vil(ac) levels
Mode Register Set command cycle time
Four activate window for 1KB page size
Four activate window for 2KB page size
ACT to internal read or write delay time
Normal operation Short calibration time
Multi-Purpose Register Recovery Time
Power-up and RESET calibration time
DQS and DQS# high-impedance time
ACT to ACT or REF command period
Normal operation Full calibration time
DQS and DQS# low-impedance time
Exit Reset from CKE HIGH to a valid
CAS# to CAS# command delay
Command and Address Timing
(Referenced from RL + BL/2)
(Referenced from RL - 1)
internal read command
PRE command period
WRITE recovery time
Self Refresh Timings
Calibration Timing
DLL locking time
Command delay
CK# rising edge
CK# rising edge
Reset Timing
locked DLL
Parameter
each input
command
page size
page size
edge
time
tHZ(DQS)
tDAL(min)
tLZ(DQS)
tIH(base)
tIS(base)
tIS(base)
tZQoper
Symbol
tDQSH
tMPRR
tDQSL
tDQSS
AC150
tZQCS
tZQinit
tDLLK
tMOD
tWTR
tMRD
tRCD
tCCD
tRRD
tRRD
tFAW
tFAW
tDSS
tDSH
tRAS
tXPR
tRTP
tIPW
tWR
tRP
tRC
tXS
max(4nCK,
DDR3/DDR3L-1333
tXPRmin.: max(5nCK, tRFC(min) + 10ns)
-0.25
Min.
-500
0.45
0.45
6ns)
See table for ADD/CMD Setup and Hold
512
620
512
256
tXSmin.: max(5nCK, tRFC(min) + 10ns)
0.2
0.2
15
30
45
64
4
4
1
-
WR + roundup(tRP / tCK(avg))
tMODmin.: max(12nCK, 15ns)
tWTRmin.: max(4nCK, 7.5ns)
tRRDmin.: max(4nCK, 7.5ns)
tRTPmin.: max(4nCK, 7.5ns)
Standard Speed Bins
Standard Speed Bins
Standard Speed Bins
Standard Speed Bins
Max.
0.55
0.55
0.25
250
250
tRTPmax.: -
tXPRmax.: -
tMODmax.:
-
-
-
tWTRmax.:
-
-
-
-
-
tRRDmax.:
-
-
-
-
-
-
tXSmax.: -
max(4nCK,
DDR3/DDR3L-1600
-0.27
Min.
-450
0.45
0.45
0.18
0.18
6ns)
512
560
512
256
15
30
40
64
4
4
1
-
Max.
0.55
0.55
0.27
225
225
-
-
-
-
-
-
-
-
-
-
-
-
-
-
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
Units
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
ns
ns
ns
ps
ps
ps
ps
63
b,16,27
13,14,f
13,14,f
Notes
29,31
30,31
c,32
c,32
e,18
b,16
b,16
22
28
23
c
e
e
e