IS46TR16128A-15HBLA2 ISSI, IS46TR16128A-15HBLA2 Datasheet - Page 26

• Manufacturer Part Number: IS46TR16128A-15HBLA2
• Description: DRAM 2G, 1.5v, 1333MT/s 128Mx16 DDR3
• Manufacturer: ISSI

Specifications of IS46TR16128A-15HBLA2

• Rohs: yes
• Data Bus Width: 16 bit
• Organization: 128 M x 16
• Package / Case: FBGA-96
• Memory Size: 2 Gbit
• Maximum Clock Frequency: 933 MHz
• Access Time: 13.125 ns
• Supply Voltage - Max: 1.575 V
• Supply Voltage - Min: 1.425 V
• Maximum Operating Current: 65 mA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT

Destination
IS43/46TR16128A, IS43/46TR16128AL,
IS43/46TR82560A, IS43/46TR82560AL
DQS - DQS# driven by the controller during leveling mode must be terminated by the DRAM based on ranks populated.
Similarly, the DQ bus driven by the DRAM must also be terminated at the controller.
One or more data bits should carry the leveling feedback to the controller across the DRAM configurations X8 and X16.
On a X16 device, both byte lanes should be leveled independently.
Therefore, a separate feedback mechanism should be available for each byte lane. The upper data bits should provide
the feedback of the upper diff_DQS(diff_UDQS) to clock relationship whereas the lower data bits would indicate the lower
diff_DQS(diff_LDQS) to clock relationship.
2.4.7.1 DRAM setting for write leveling & DRAM termination function in that mode
DRAM enters into Write leveling mode if A7 in MR1 set ’High’ and after finishing leveling, DRAM exits from write leveling
mode if A7 in MR1 set ’Low’. Note that in write leveling mode, only DQS/DQS# terminations are activated and deactivated
via ODT pin, unlike normal operation.
MR setting involved in the leveling procedure
DRAM termination function in the leveling mode
NOTE: In Write Leveling Mode with its output buffer disabled (MR1[bit7] = 1 with MR1[bit12] = 1) all RTT_Nom settings are allowed; in Write Leveling
Mode with its output buffer enabled (MR1[bit7] = 1 with MR1[bit12] = 0) only RTT_Nom settings of RZQ/2, RZQ/4 and RZQ/6 are allowed.
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00A
11/14/2012
Source
diff_DQS
diff_DQS
diff_DQS
CK#
CK
DQ
DQ
Output buffer mode (Qoff)
CK#
CK
Write leveling enable
ODT pin @DRAM
De-asserted
Tn
Function
Asserted
Push DQS to capture
T0
0-1 transition
0 or 1
0 or 1
T0
T1
T1
Figure 2.4.7 Write Leveling Concept
T2
0
T2
DQS/DQS# termination
MR1
1
T3
A12
A7
Off
On
T3
T4
0
T4
Enable
T5
1
0
1
T5
DQs termination
T6
0
Off
Off
Disable
T6
1
0
1
T7
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