IS46TR16128A-15HBLA2 ISSI, IS46TR16128A-15HBLA2 Datasheet - Page 10

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IS46TR16128A-15HBLA2

Manufacturer Part Number
IS46TR16128A-15HBLA2
Description
DRAM 2G, 1.5v, 1333MT/s 128Mx16 DDR3
Manufacturer
ISSI

Specifications of IS46TR16128A-15HBLA2

Rohs
yes
Data Bus Width
16 bit
Organization
128 M x 16
Package / Case
FBGA-96
Memory Size
2 Gbit
Maximum Clock Frequency
933 MHz
Access Time
13.125 ns
Supply Voltage - Max
1.575 V
Supply Voltage - Min
1.425 V
Maximum Operating Current
65 mA
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Command
Command
Address
Settings
Address
Settings
IS43/46TR16128A, IS43/46TR16128AL,
IS43/46TR82560A, IS43/46TR82560AL
The MRS command to Non-MRS command delay, tMOD, is require for the DRAM to update the features except DLL
reset, and is the minimum time required from an MRS command to a non-MRS command excluding NOP and DES shown
as the following figure.
The mode register contents can be changed using the same command and timing requirements during normal operation
as long as the DRAM is in idle state, i.e., all banks are in the precharged state with tRP satisfied, all data bursts are
completed and CKE is high prior to writing into the mode register. If the RTT_NOM Feature is enabled in the Mode
Register prior and/or after an MRS Command, the ODT Signal must continuously be registered LOW ensuring RTT is in
an off State prior to the MRS command. The ODT Signal maybe registered high after tMOD has expired. If the RTT_NOM
Feature is disabled in the Mode Register prior and after an MRS command, the ODT Signal can be registered either LOW
or HIGH before, during and after the MRS command. The mode registers are divided into various fields depending on the
functionality and/or modes.
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00A
11/14/2012
CKE
ODT
ODT
ODT
ODT
CKE
CK#
CK
CK#
CK
RTT_Nom ENABLED prior and/or after MRS command
RTT_Nom DISABLED prior and after MRS command
RTT_Nom ENABLED prior and/or after MRS command
RTT_Nom DISABLED prior and after MRS command
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Old Settings
Valid
Valid
Valid
Valid
Old Settings
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
ODTLoff + 1
ODTLoff + 1
MRS
Valid
Valid
MRS
Valid
Valid
Figure 2.3.1b tMOD Timing
NOP/
Valid
Valid
DEC
Figure2.3.1a tMRD Timing
NOP/
Valid
Valid
DEC
tMRD
NOP/
Valid
Valid
DEC
NOP/
Valid
Valid
DEC
MRS
Valid
Valid
tMOD
NOP/
Valid
Valid
DEC
NOP/
Valid
Valid
DEC
NOP/
Valid
Valid
DEC
tMRD
Valid
Valid
NOP/
Valid
DEC
NOP/
Valid
DEC
( (
) )
( (
) )
Time
Break
Time
Break
Valid
Valid
Valid
Valid
Valid
Valid
New Settings
New Settings
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
DON’T
CARE
DON’T
CARE
10

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