IS46TR16128A-15HBLA2 ISSI, IS46TR16128A-15HBLA2 Datasheet - Page 59

• Manufacturer Part Number: IS46TR16128A-15HBLA2
• Description: DRAM 2G, 1.5v, 1333MT/s 128Mx16 DDR3
• Manufacturer: ISSI

Specifications of IS46TR16128A-15HBLA2

• Rohs: yes
• Data Bus Width: 16 bit
• Organization: 128 M x 16
• Package / Case: FBGA-96
• Memory Size: 2 Gbit
• Maximum Clock Frequency: 933 MHz
• Access Time: 13.125 ns
• Supply Voltage - Max: 1.575 V
• Supply Voltage - Min: 1.425 V
• Maximum Operating Current: 65 mA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT

IS43/46TR16128A, IS43/46TR16128AL,
IS43/46TR82560A, IS43/46TR82560AL
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00A
11/14/2012
Delay from start of internal write transaction to
DQS, DQS# differential input high pulse width
Cumulative error across n = 13, 14 . . . 49, 50
Data setup time to DQS, DQS# referenced to
Data setup time to DQS, DQS# referenced to
DQS, DQS# differential input low pulse width
Data hold time from DQS, DQS# referenced
DQ and DM Input pulse width for each input
DQS, DQS# falling edge hold time from CK,
DQS, DQS# rising edge output access time
Internal READ Command to PRECHARGE
Mode Register Set command update delay
DQS, DQS# differential WRITE Postamble
DQS, DQS# falling edge setup time to CK,
DQS, DQS# rising edge to CK, CK# rising
DQS, DQS# differential READ Postamble
DQS, DQS# differential WRITE Preamble
DQS, DQS# to DQ skew, per group, per
DQS, DQS# differential output high time
DQS,DQS# differential READ Preamble
Mode Register Set command cycle time
DQ high impedance time from CK, CK#
DQS, DQS# differential output low time
ACT to internal read or write delay time
DQ low-impedance time from CK, CK#
DQ output hold time from DQS, DQS#
DQS and DQS# high-impedance time
ACT to ACT or REF command period
DQS and DQS# low-impedance time
Cumulative error across 12 cycles
CAS# to CAS# command delay
Command and Address Timing
(Referenced from RL + BL/2)
to Vih(dc) / Vil(dc) levels
(Referenced from RL - 1)
internal read command
PRE command period
Vih(ac) / Vil(ac) levels
Vih(ac) / Vil(ac) levels
WRITE recovery time
from rising CK, CK#
Data Strobe Timing
DLL locking time
Command delay
CK# rising edge
CK# rising edge
Data Timing
Parameter
access
cycles
edge
tERR(12per)
tERR(nper)
tDS(base)
tDS(base)
tDH(base)
tHZ(DQS)
tLZ(DQS)
tDQSCK
tHZ(DQ)
tLZ(DQ)
Symbol
tDQSQ
tWPRE
DC100
tWPST
tDQSH
tDQSS
AC175
AC150
tRPRE
tDQSL
tDIPW
tRPST
tDLLK
tWTR
tMRD
tMOD
tQSH
tRCD
tCCD
tQSL
tDSS
tDSH
tRTP
tWR
tQH
tRC
tRP
tERR(nper)min = (1 + 0.68ln(n)) * tJIT(per)min
DDR3/DDR3L-800
-0.25
-269
-800
-400
-800
Min.
0.38
0.38
0.38
0.45
0.45
600
512
0.9
0.3
0.9
0.3
0.2
0.2
15
4
4
-
-
-
See table for Data Setup and Hold
tERR(nper)max = (1 + 0.68ln(n)) *
tMODmin.: max(12nCK, 15ns)
tWTRmin.: max(4nCK, 7.5ns)
tRTPmin.: max(4nCK, 7.5ns)
Standard Speed Bins
Standard Speed Bins
Standard Speed Bins
Max.
Note
Note
0.55
0.55
0.25
269
200
400
400
400
400
400
tJIT(per)max
tRTPmax.: -
tMODmax.:
-
-
-
-
-
-
-
-
-
tWTRmax.:
-
-
-
DDR3/DDR3L-1066
-0.25
Min.
-242
0.38
-600
0.38
0.38
-300
-600
0.45
0.45
490
512
0.9
0.3
0.2
0.2
19
11
15
4
4
-
-
-
Max.
0.55
0.55
0.25
242
150
300
300
300
300
300
0.9
0.3
-
-
-
-
-
-
-
-
-
-
-
-
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
Units
Note
Note
nCK
nCK
nCK
ps
ps
ps
ps
ps
ps
ps
ps
ps
ns
59
13,19,g
11,13,g
13,14,f
13,14,f
13,14,f
13,14,f
Notes
29,31
30,31
13,g
d,17
d,17
d,17
13,g
13,g
c,32
c,32
e,18
e,18
13,f
24
13
28
c
e
e
e
e