IS46TR16128A-15HBLA2 ISSI, IS46TR16128A-15HBLA2 Datasheet - Page 25

• Manufacturer Part Number: IS46TR16128A-15HBLA2
• Description: DRAM 2G, 1.5v, 1333MT/s 128Mx16 DDR3
• Manufacturer: ISSI

Specifications of IS46TR16128A-15HBLA2

• Rohs: yes
• Data Bus Width: 16 bit
• Organization: 128 M x 16
• Package / Case: FBGA-96
• Memory Size: 2 Gbit
• Maximum Clock Frequency: 933 MHz
• Access Time: 13.125 ns
• Supply Voltage - Max: 1.575 V
• Supply Voltage - Min: 1.425 V
• Maximum Operating Current: 65 mA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT

IS43/46TR16128A, IS43/46TR16128AL,
IS43/46TR82560A, IS43/46TR82560AL
2.4.6. Input clock frequency change
Once the DDR3 SDRAM is initialized, the DDR3 SDRAM requires the clock to be “stable” during almost all states of
normal operation. This means that, once the clock frequency has been set and is to be in the “stable state”, the clock
period is not allowed to deviate except for what is allowed for by the clock jitter and SSC (spread spectrum clocking)
specifications.
The input clock frequency can be changed from one stable clock rate to another stable clock rate under two conditions:
(1) Self-Refresh mode and (2) Precharge Power-down mode. Outside of these two modes, it is illegal to change the clock
frequency.
For the first condition, once the DDR3 SDRAM has been successfully placed in to Self-Refresh mode and tCKSRE has
been satisfied, the state of the clock becomes a don’t care. Once a don’t care, changing the clock frequency is
permissible, provided the new clock frequency is stable prior to tCKSRX. When entering and exiting Self-Refresh mode
for the sole purpose of changing the clock frequency, the Self-Refresh entry and exit specifications must still be met.
The DDR3 SDRAM input clock frequency is allowed to change only within the minimum and maximum operating
frequency specified for the particular speed grade. Any frequency change below the minimum operating frequency would
require the use of DLL_on- mode -> DLL_off -mode transition sequence, refer to “DLL on/off switching procedure”.
The second condition is when the DDR3 SDRAM is in Precharge Power-down mode (either fast exit mode or slow exit
mode). If the RTT_NOM feature was enabled in the mode register prior to entering Precharge power down mode, the
ODT signal must continuously be registered LOW ensuring RTT is in an off state. If the RTT_NOM feature was disabled in
the mode register prior to entering Precharge power down mode, RTT will remain in the off state. The ODT signal can be
registered either LOW or HIGH in this case. A minimum of tCKSRE must occur after CKE goes LOW before the clock
frequency may change. The DDR3 SDRAM input clock frequency is allowed to change only within the minimum and
maximum operating frequency specified for the particular speed grade. During the input clock frequency change, ODT
and CKE must be held at stable LOW levels. Once the input clock frequency is changed, stable new clocks must be
provided to the DRAM tCKSRX before Precharge Power-down may be exited; after Precharge Power-down is exited and
tXP has expired, the DLL must be RESET via MRS. Depending on the new clock frequency, additional MRS commands
may need to be issued to appropriately set the WR, CL, and CWL with CKE continuously registered high. During DLL re-
lock period, ODT must remain LOW and CKE must remain HIGH. After the DLL lock time, the DRAM is ready to operate
with new clock frequency.
2.4.7 Write leveling
For better signal integrity, the DDR3 memory module adopted fly-by topology for the commands, addresses, control
signals, and clocks. The fly-by topology has benefits from reducing number of stubs and their length, but it also causes
flight time skew between clock and strobe at every DRAM on the DIMM. This makes it difficult for the Controller to
maintain tDQSS, tDSS, and tDSH specification. Therefore, the DDR3 SDRAM supports a ‘write leveling’ feature to allow
the controller to compensate for skew.
The memory controller can use the ‘write leveling’ feature and feedback from the DDR3 SDRAM to adjust the DQS -
DQS# to CK - CK# relationship. The memory controller involved in the leveling must have adjustable delay setting on
DQS - DQS# to align the rising edge of DQS - DQS# with that of the clock at the DRAM pin. The DRAM asynchronously
feeds back CK - CK#, sampled with the rising edge of DQS - DQS#, through the DQ bus. The controller repeatedly delays
DQS - DQS# until a transition from 0 to 1 is detected. The DQS - DQS# delay established though this exercise would
ensure tDQSS specification.
Besides tDQSS, tDSS and tDSH specification also needs to be fulfilled. One way to achieve this is to combine the actual
tDQSS in the application with an appropriate duty cycle and jitter on the DQS - DQS# signals. Depending on the actual
tDQSS in the application, the actual values for tDQSL and tDQSH may have to be better than the absolute limits provided
in the chapter "AC Timing Parameters" in order to satisfy tDSS and tDSH specification. A conceptual timing of this
scheme is shown in Figure 2.4.7.
Integrated Silicon Solution, Inc. – www.issi.com –
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Rev. 00A
11/14/2012