IS46TR16128A-15HBLA2 ISSI, IS46TR16128A-15HBLA2 Datasheet - Page 61

• Manufacturer Part Number: IS46TR16128A-15HBLA2
• Description: DRAM 2G, 1.5v, 1333MT/s 128Mx16 DDR3
• Manufacturer: ISSI

Specifications of IS46TR16128A-15HBLA2

• Rohs: yes
• Data Bus Width: 16 bit
• Organization: 128 M x 16
• Package / Case: FBGA-96
• Memory Size: 2 Gbit
• Maximum Clock Frequency: 933 MHz
• Access Time: 13.125 ns
• Supply Voltage - Max: 1.575 V
• Supply Voltage - Min: 1.425 V
• Maximum Operating Current: 65 mA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT

IS43/46TR16128A, IS43/46TR16128AL,
IS43/46TR82560A, IS43/46TR82560AL
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00A
11/14/2012
Timing of WR command to Power Down entry
Timing of WR command to Power Down entry
ODT high time without write command or with
Timing of RD/RDA command to Power Down
DQS/DQS# delay after write leveling mode is
Write leveling setup time from rising CK, CK#
ODT high time with Write command and BL8
Timing of PRE or PREA command to Power
RTT_Nom and RTT_WR turn-off time from
DQS# crossing to rising CK, CK# crossing
Timing of WRA command to Power Down
Timing of WRA command to Power Down
Asynchronous RTT turn-on delay (Power-
Asynchronous RTT turn-off delay (Power-
Timing of MRS command to Power Down
Timing of ACT command to Power Down
Timing of REF command to Power Down
Write leveling hold time from rising DQS,
First DQS/DQS# rising edge after write
crossing to rising DQS, DQS# crossing
entry (BL8OTF, BL8MRS, BC4OTF)
(BL8OTF, BL8MRS, BC4OTF)
leveling mode is programmed
RTT dynamic change skew
Write leveling output delay
Write leveling output error
write command and BC4
Down with DLL frozen)
Down with DLL frozen)
Write Leveling Timings
ODTLoff reference
entry (BC4MRS)
ODT Timings
programmed
RTT turn-on
Down entry
(BC4MRS)
Parameter
Parameter
entry
entry
entry
entry
tWRAPDEN
tWRAPDEN
tMRSPDEN
tWLDQSEN
tACTPDEN
tREFPDEN
tWRPDEN
tWRPDEN
tRDPDEN
tPRPDEN
tWLMRD
tAONPD
tAOFPD
ODTH4
ODTH8
Symbol
Symbol
tWLOE
tWLO
tAON
tWLS
tWLH
tAOF
tADC
DDR3/DDR3L-800
tWRPDENmin.: WL + 4 + (tWR / tCK(avg))
tWRPDENmin.: WL + 2 + (tWR / tCK(avg))
Min.
-400
Min.
325
325
0.3
0.3
40
25
2
2
0
0
DDR3-800
tWRAPDENmin.: WL + 2 +WR + 1
tWRAPDENmin.: WL+4+WR+1
tMRSPDENmin.: tMOD(min)
tRDPDENmin.: RL+4+1
tWRAPDENmax.: -
tWRAPDENmax.: -
tMRSPDENmax.: -
tACTPDENmax.: -
tREFPDENmax.: -
tACTPDENmin.: 1
tREFPDENmin.: 1
Max.
tWRPDENmax.: -
tWRPDENmax.: -
tRDPDENmax.: -
tPRPDENmin.: 1
tPRPDENmax.: -
Max.
ODTH4max.: -
ODTH8max.: -
ODTH4min.: 4
ODTH8min.: 6
400
8.5
8.5
0.7
0.7
9
2
-
-
-
-
DDR3/DDR3L-1066
Min.
Min.
-300
245
245
0.3
0.3
40
25
DDR3-1066
2
2
0
0
Max.
Max.
300
8.5
8.5
0.7
0.7
9
2
-
-
-
-
tCK(avg)
tCK(avg)
Units
Units
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
ns
ns
ps
ps
ps
ns
ns
61
Notes
Notes
20,21
20
20
10
10
7,f
8,f
9
9
3
3
f