IS46TR16128A-15HBLA2 ISSI, IS46TR16128A-15HBLA2 Datasheet - Page 15

• Manufacturer Part Number: IS46TR16128A-15HBLA2
• Description: DRAM 2G, 1.5v, 1333MT/s 128Mx16 DDR3
• Manufacturer: ISSI

Specifications of IS46TR16128A-15HBLA2

• Rohs: yes
• Data Bus Width: 16 bit
• Organization: 128 M x 16
• Package / Case: FBGA-96
• Memory Size: 2 Gbit
• Maximum Clock Frequency: 933 MHz
• Access Time: 13.125 ns
• Supply Voltage - Max: 1.575 V
• Supply Voltage - Min: 1.425 V
• Maximum Operating Current: 65 mA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT

IS43/46TR16128A, IS43/46TR16128AL,
IS43/46TR82560A, IS43/46TR82560AL
2.3.4 Mode Register MR2
The Mode Register MR2 stores the data for controlling refresh related features, Rtt_WR impedance, and CAS write
latency. The Mode Register 2 is written by asserting low on CS#, RAS#, CAS#, WE#, high on BA1 and low on BA0 and
BA2, while controlling the states of address pins according to the below.
* 1 : A5, A8, A11 ~ A14 must be programmed to 0 during MRS.
* 2 : The Rtt_WR value can be applied during writes even when Rtt_Nom is disabled. During write leveling, Dynamic ODT is not available
2.3.4.1 Partial Array Self-Refresh (PASR)
If PASR (Partial Array Self-Refresh) is enabled, data located in areas of the array beyond the specified address range
shown in Figure 2.3.4 will be lost if Self-Refresh is entered. Data integrity will be maintained if tREFI conditions are met
and no Self-Refresh command is issued.
2.3.4.2 CAS Write Latency (CWL)
The CAS Write Latency is defined by MR2 (bits A3-A5), as shown in Figure 2.3.4. CAS Write Latency is the delay, in clock
cycles, between the internal Write command and the availability of the first bit of input data. DDR3 SDRAM does not
support any half-clock latencies. The overall Write Latency (WL) is defined as Additive Latency (AL) + CAS Write Latency
(CWL); WL = AL + CWL. For more information on the supported CWL and AL settings based on the operating clock
frequency, refer to “Standard Speed Bins”.
2.3.4.3 Auto Self-Refresh (ASR) and Self-Refresh Temperature (SRT)
For more details refer to “Extended Temperature Usage”. DDR3 SDRAMs support Self-Refresh operation at all supported
temperatures. Applications requiring Self-Refresh operation in the Extended Temperature Range must use the ASR
function or program the SRT bit appropriately.
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00A
11/14/2012
BA1 BA0
BA2 BA1 BA0
A10
A7
A6
0
0
1
0
1
0
0
1
1
0
0
1
1
A9
1
0
1
0
1
0
1
0
1
Manual SR Reference (SRT)
Self-Refresh Temperature (SRT) Range
Auto Self-Refresh (ASR)
Extended operating temperature range
Normal operating temperature range
0
Dynamic ODT off (Write does not affect Rtt value)
MR Select
ASR enable
MR0
MR1
MR2
MR3
A14-A13
0*
1
Rtt_WR
Reserved
RZQ/4
RZQ/2
A12
*2
A11
A10
Rtt_WR
Figure 2.3.4 MR2 Definition
A9
0*
A8
A2
0
0
0
0
1
1
1
1
1
SRT ASR
A7
A1
0
0
1
1
0
0
1
1
A6
A0
A5
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
A5
A4
0
0
1
1
0
0
1
1
3/4 Array (BA[2:0] = 010,011,100,101,110, & 111)
CWL
HalfArray (BA[2:0] = 100, 101, 110, &111)
A4
A3
HalfArray (BA[2:0]=000,001,010, &011)
0
1
0
1
0
1
0
1
Quarter Array (BA[2:0]=000, & 001)
Partial Array Self-Refresh (Optional)
Quarter Array (BA[2:0]=110, &111)
A3
1/8th Array (BA[2:0] = 000)
1/8th Array (BA[2:0]=111)
10 (1.07 ns > tCK(avg)  0.935 ns)
6 (2.5 ns > tCK(avg)  1.875 ns)
7 (1.875 ns > tCK(avg)  1.5 ns)
9 (1.25 ns > tCK(avg)  1.07ns)
8 (1.5 ns > tCK(avg)  1.25 ns)
A2
CAS write Latency (CWL)
Full Array
5 (tCK(avg)  2.5 ns)
PASR
A1
Reserved
Reserved
A0
Address Field
Mode Register 2
.
15