NT5DS16M16CS NANOAMP [NanoAmp Solutions, Inc.], NT5DS16M16CS Datasheet - Page 63

• Manufacturer Part Number: NT5DS16M16CS
• Description: 256Mb DDR Synchronous DRAM
• Manufacturer: NANOAMP [NanoAmp Solutions, Inc.]

NanoAmp Solutions, Inc.
DOC # 14-02-044 Rev A ECN # 01-1116
The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com
Data Input (Write)
Data Output (Read)
DI n = Data In for column n.
3 subsequent elements of data in are applied in programmed order following DI n.
DQS
DQ
CK
CK
t
and not to the data strobe (DQS) duty cycle.
Data Output hold time from Data Strobe is shown as t
for that given clock cycle. Note correlation of t
t
HP
DQSQ
is the half cycle pulse width for each half cycle clock. t
t
HP
DQS
(max) occurs when DQS is the earliest among DQS and DQ signals to transition.
DM
DQ
(Timing Burst Length = 4)
(Timing Burst Length = 4)
t
HP
t
t
DS
DS
t
DSL
t
t
HP
DQSQ
DI n
t
DSH
t
t
HP
DH
DH
t
t
t
DQSQ
QH1
HP1
to t
QH
QH
in the diagram above (t
. t
HP
QH
t
is referenced to the clock duty cycle only
QH2
t
is a function of the clock high or low time (t
t
DQSQ
HP2
NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT
NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS
t
QH3
t
t
HP3
DQSQ
HP1
to t
QH1
t
QH4
, etc.).
t
HP4
Don’t Care
HP
)
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