NT5DS16M16CS NANOAMP [NanoAmp Solutions, Inc.], NT5DS16M16CS Datasheet - Page 48

• Manufacturer Part Number: NT5DS16M16CS
• Description: 256Mb DDR Synchronous DRAM
• Manufacturer: NANOAMP [NanoAmp Solutions, Inc.]

NanoAmp Solutions, Inc.
Truth Table 3: Current State Bank n - Command to Bank n (Same Bank)
DOC # 14-02-044 Rev A ECN # 01-1116
The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com
10. Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with
11. Requires appropriate DM masking.
(Auto Precharge
(Auto Precharge
1. This table applies when CKE n-1 was high and CKE n is high (see Truth Table 2: Clock Enable (CKE) and after t
2. This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those allowed
3. Current state definitions:
4. The following states must not be interrupted by a command issued to the same bank.
5. The following states must not be interrupted by any executable command; Deselect or NOP commands must be applied on each positive
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle.
8. May or may not be bank-specific; if all/any banks are to be precharged, all/any must be in a valid state for precharging.
9. Not bank-specific; Burst terminate affects the most recent Read burst, regardless of bank.
Current State
Row Active
Disabled)
Disabled)
met (if the previous state was self refresh).
to be issued to that bank when in that state. Exceptions are covered in the notes below.
Idle:
Row Active:
Read:
Write:
Precharging:
Row Activating: Starts with registration of an Active command and ends when t
Read w/Auto Precharge Enabled: Starts with registration of a Read command with Auto Precharge enabled and ends when t
Write w/Auto Precharge Enabled: Starts with registration of a Write command with Auto Precharge enabled and ends when t
Deselect or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these
clock edge during these states.
Refreshing:
Accessing Mode Register: Starts with registration of a Mode Register Set command and ends when t
Precharging All: Starts with registration of a Precharge All command and ends when t
Auto Precharge disabled.
Read
Write
Any
Idle
CS
H
L
L
L
L
L
L
L
L
L
L
L
L
L
The bank has been precharged, and t
A row in the bank has been activated, and t
progress.
A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Starts with registration of a Precharge command and ends when t
state.
active” state.
met. Once t
met. Once t
states. Allowable commands to the other bank are determined by its current state and according to Truth Table 4.
Starts with registration of an Auto Refresh command and ends when t
in the “all banks idle” state.
met, the DDR SDRAM is in the “all banks idle” state.
state.
RAS
X
H
H
H
H
H
H
H
L
L
L
L
L
L
RP
RP
CAS
is met, the bank is in the idle state.
is met, the bank is in the idle state.
H
H
H
H
H
H
X
L
L
L
L
L
L
L
WE
X
H
H
H
H
H
H
L
L
L
L
L
L
L
Mode Register Set
Burst Terminate
No Operation
Auto Refresh
RP
Command
Precharge
Precharge
Precharge
Deselect
Active
has been met.
Read
Write
Read
Read
Write
RCD
has been met. No data bursts/accesses and no register accesses are in
NOP. Continue previous operation
NOP. Continue previous operation
Select and activate row
Select column and start Read burst
Select column and start Write burst
Deactivate row in bank(s)
Select column and start new Read burst
Truncate Read burst, start Precharge
Burst Terminate
Select column and start Read burst
Select column and start Write burst
Truncate Write burst, start Precharge
NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT
NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS
RCD
RP
is met. Once t
is met. Once t
RP
RFC
is met. Once t
is met. Once t
Action
RCD
RP
MRD
is met, the bank is in the “row
is met, the bank is in the idle
RP
RFC
has been met. Once t
is met, all banks is in the idle
is met, the DDR SDRAM is
XSNR /
t
XSRD
RP
RP
1-6, 10, 11
1-6, 8, 11
has been
1-6, 10
1-6, 10
1-6, 10
1-6, 10
Notes
has been
has been
1-6, 8
1-6, 8
1-6, 9
MRD
1-6
1-6
1-6
1-7
1-7
is
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