NT5DS16M16CS NANOAMP [NanoAmp Solutions, Inc.], NT5DS16M16CS Datasheet - Page 58

• Manufacturer Part Number: NT5DS16M16CS
• Description: 256Mb DDR Synchronous DRAM
• Manufacturer: NANOAMP [NanoAmp Solutions, Inc.]

NanoAmp Solutions, Inc.
AC Input Operating Conditions
(0 °C
I
(0 °C
DOC # 14-02-044 Rev A ECN # 01-1116
The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com
Device testing was performed with x16 wide devices.
DD
Symbol
I
I
I
I
I
I
Symbol
1. Input slew rate = 1V/ns
2. Inputs are not recognized as valid until V
3. V
4. The value of V
1. I
2. Enables on-chip refresh and address counters.
V
V
DD4W
V
V
I
I
DD2P
DD2N
DD3P
DD3N
DD4R
I
I
I
DD0
DD1
DD5
DD6
DD7
IH(AC)
ID(AC)
IX(AC)
IL(AC)
Specifications and Conditions
DD
T
T
ID
A
A
specifications are tested after the device is properly initialized.
is the magnitude of the difference between the input level on CK and the input level on CK.
Operating Current: one bank; active / precharge; t
and DQS inputs changing twice per clock cycle; address and control inputs
changing once per clock cycle
Operating Current: one bank; active / read / precharge; Burst = 2; t
t
per clock cycle
Precharge Power Down Standby Current: all banks idle; Power Down
mode; CKE
Idle Standby Current: CS
address and control inputs changing once per clock cycle
Active Power Down Standby Current: one bank active; Power Down
mode;
CKE
Active Standby Current: one bank; active / precharge; CS
CKE
twice per clock cycle; address and control inputs changing once per clock
cycle
Operating Current: one bank; Burst = 2; reads; continuous burst; address
and control inputs changing once per clock cycle; DQ and DQS outputs
changing twice per clock cycle; CL = 2.5; I
Operating Current: one bank; Burst = 2; writes; continuous burst; address
and control inputs changing once per clock cycle; DQ and DQS inputs
changing twice per clock cycle; CL = 2.5
Auto-Refresh Current: t
Self-Refresh Current: CKE
Operating current: four bank; four bank interleaving with BL = 4, address
and control inputs randomly changing; 50% of data changing at every trans-
fer;
t
70 C V
70 C V
RC
RC
Input High (Logic 1) Voltage, DQ, DQS, and DM Signals
Input Low (Logic 0) Voltage, DQ, DQS, and DM Signals
Input Differential Voltage, CK and CK Inputs
Input Crossing Point Voltage, CK and CK Inputs
(min); CL = 2.5; I
= t
V
V
DDQ
DDQ
RC
IL
IH
IX
(min); I
(max)
(min); t
= V
= V
is expected to equal 0.5*V
V
DD
DD
IL
= 2.5V
= 2.5V
(max)
OUT
RC
OUT
= t
= 0mA.
RAS
= 0mA; address and control inputs changing once
RC
0.2V (DDR333); V
0.2V (DDR333); V
Parameter/Condition
(max); DQ, DM, and DQS inputs changing
= t
Parameter/Condition
V
0.2V
IH
RFC
(min); all banks idle; CKE
(min)
REF
DDQ
stabilizes.
DDQ
DDQ
OUT
of the transmitting device and must track variations in the DC level of the same.
= V
= V
= 0mA
DD
DD
RC
= 2.6V
= 2.6V
= t
RC
0.1V (DDR400); See AC Characteristics)
0.1V (DDR400); See AC Characteristics)
(min); DQ, DM,
V
V
IH
IH
(min);
(min);
RC
=
NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT
NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS
DDR400
t
CK
0.5*V
(5T)
105
119
124
246
V
76
79
29
11
46
=5ns
4
2
REF
0.62
DDQ
Min
+ 0.31
DDR333
t
CK
(6K)
118
207
0.2 0.5*V
68
72
25
10
39
87
98
=6ns
4
2
V
V
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
REF
DDQ
Max
DDQ
+ 0.6
0.31
Notes
1, 2
0.2
1
1
1
1
1
1
1
1
1
1
Unit
V
V
V
V
1, 2, 3
1, 2, 4
Notes
1, 2
1, 2
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