NT5DS16M16CS NANOAMP [NanoAmp Solutions, Inc.], NT5DS16M16CS Datasheet - Page 49

• Manufacturer Part Number: NT5DS16M16CS
• Description: 256Mb DDR Synchronous DRAM
• Manufacturer: NANOAMP [NanoAmp Solutions, Inc.]

NanoAmp Solutions, Inc.
Truth Table 4: Current State Bank n - Command to Bank m (Different bank)
DOC # 14-02-044 Rev A ECN # 01-1116
The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com
(Part 1 of 2)
10. The Read with Auto Precharge enabled or Write with Auto Precharge enabled states can each be broken into two parts: the access
(Auto Precharge
(Auto Precharge
Row Activating,
1. This table applies when CKE n-1 was high and CKE n is high (see Truth Table 2: Clock Enable (CKE) and after t
2. This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are
3. Current state definitions:
4. Auto Refresh and Mode Register Set commands may only be issued when all banks are idle.
5. A Burst Terminate command cannot be issued to another bank; it applies to the bank represented by the current state only.
6. All states and sequences not shown are illegal or reserved.
7. Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with
8. Requires appropriate DM masking.
9. A Write command may be applied after the completion of data output.
Current State
Precharging
Disabled)
Disabled)
Active, or
met (if the previous state was self refresh).
those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are cov-
ered in the notes below.
Idle:
Row Active:
Read:
Write:
Read with Auto Precharge Enabled: See note 10.
Write with Auto Precharge Enabled: See note 10.
Auto Precharge disabled.
period and the precharge period. For Read with Auto Precharge, the precharge period is defined as if the same burst was executed with
Auto Precharge disabled and then followed with the earliest possible Precharge command that still accesses all of the data in the burst.
For Write with Auto Precharge, the precharge period begins when t
access period starts with registration of the command and ends where the precharge period (or t
of the Read with Auto Precharge Enabled or Write with Auto Precharge Enabled states, Active, Precharge, Read, and Write commands to
the other bank may be applied; during the access period, only Active and Precharge commands to the other bank may be applied. In
either case, all other related limitations apply (e.g. contention between Read data and Write data must be avoided).
Read
Write
Any
Idle
CS
H
L
X
L
L
L
L
L
L
L
L
L
L
L
The bank has been precharged, and t
in progress.
A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
A row in the bank has been activated, and t
RAS
X
H
X
H
H
H
H
H
L
L
L
L
L
L
CAS
H
H
H
H
H
H
H
X
X
L
L
L
L
L
WE
X
H
X
H
H
H
H
H
H
L
L
L
L
L
Any Command Otherwise
Allowed to Bank m
No Operation
RP
Command
Precharge
Precharge
Precharge
Deselect
has been met.
Active
Active
Active
Read
Write
Read
Read
Write
RCD
has been met. No data bursts/accesses and no register accesses are
WR
ends, with t
NOP/continue previous operation
NOP/continue previous operation
Select and activate row
Select column and start Read burst
Select column and start Write burst
Select and activate row
Select column and start new Read burst
Select and activate row
Select column and start Read burst
Select column and start new Write burst
NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT
NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS
WR
measured as if Auto Precharge was disabled. The
RP
Action
) begins. During the precharge period
XSNR /
t
XSRD
has been
Notes
1-6
1-6
1-6
1-6
1-7
1-7
1-6
1-6
1-7
1-6
1-6
1-8
1-7
1-6
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