NT5DS16M16CS NANOAMP [NanoAmp Solutions, Inc.], NT5DS16M16CS Datasheet - Page 47

• Manufacturer Part Number: NT5DS16M16CS
• Description: 256Mb DDR Synchronous DRAM
• Manufacturer: NANOAMP [NanoAmp Solutions, Inc.]

NanoAmp Solutions, Inc.
Truth Table 2: Clock Enable (CKE)
DOC # 14-02-044 Rev A ECN # 01-1116
The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com
1. CKE n is the logic state of CKE at clock edge n: CKE n-1 was the state of CKE at the previous clock edge.
2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.
3. Command n is the command registered at clock edge n, and action n is a result of command n.
4. All states and sequences not shown are illegal or reserved.
1. Deselect or NOP commands should be issued on any clock edges occurring during the Self Refresh Exit (t
200 clock cycles are needed before applying a read command to allow the DLL to lock to the input clock.
Bank(s) Active
All Banks Idle
All Banks Idle
Current State
Power Down
Power Down
Self Refresh
Self Refresh
Previous
CKE n-1
Cycle
H
H
H
H
L
L
L
L
Current
CKEn
Cycle
H
H
H
L
L
L
L
L
Bank n - Command to Bank n (Same
See “Truth Table 3: Current State
Bank)” on page 48
Deselect or NOP
Deselect or NOP
Deselect or NOP
Deselect or NOP
Auto Refresh
Command n
X
X
NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT
NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS
Maintain Self-Refresh
Exit Self-Refresh
Maintain Power Down
Exit Power Down
Precharge Power Down Entry
Self Refresh Entry
Active Power Down Entry
Action n
XSNR
) period. A minimum of
Notes
1
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