CN8330EPD CONEXANT [Conexant Systems, Inc], CN8330EPD Datasheet - Page 94

• Manufacturer Part Number: CN8330EPD
• Description: DS3/E3 Framer with 52 Mbps HDLC Controller
• Manufacturer: CONEXANT [Conexant Systems, Inc]

Appendix A Multimegabit HDLC Formatter
Control Registers
0x00—Mode Control Register (CR00)
LineLp
SourceLp
0x04—Feature Control Register (CR04)
The Feature Control Register is provided to enable or disable miscellaneous features in the CN8330 Framer.
ParaEn
A-10
Control Registers
LineLp
Rsvd
7
7
SourceLP
Line Loopback Enable—Set to enable the loopback in the external direction. This loopback
connects the received data stream before B3ZS/HDB3 decoding to the transmitter outputs. The
received data is still presented to all receiver blocks and is present on the receiver output pins.
Source Loopback Enable—Set to enable the loopback in the internal direction. This loopback
connects the encoded transmitter data and clock directly to the receiver. Transmission of data
on the line is not affected by this loopback.
Parallel Data Enable—Set high to enable the PPDL transmitter and receiver as the source and
sink for data. Eight-bit data bytes are provided on the TDAT[7:0] and RDAT[7:0] buses for the
PPDL transmitter and receiver. This bit must be set to 1 for operation as an HDLC formatter.
Rsvd
6
6
NOTE:
NOTE:
Rsvd
Rsvd
5
5
Rsvd bits in Control Registers must be set to zero.
Rsvd bits in Control Registers must be set to zero.
Rsvd
Rsvd
4
4
Conexant
ParaEn
Rsvd
3
3
DS3/E3 Framer with 52 Mbps HDLC Controller
Rsvd
Rsvd
2
2
Rsvd
Rsvd
1
1
CN8330
Rsvd
Rsvd
100441E
0
0