CN8330EPD CONEXANT [Conexant Systems, Inc], CN8330EPD Datasheet - Page 88

• Manufacturer Part Number: CN8330EPD
• Description: DS3/E3 Framer with 52 Mbps HDLC Controller
• Manufacturer: CONEXANT [Conexant Systems, Inc]

Appendix A Multimegabit HDLC Formatter
A.2 Block and Logic Diagrams
Figure A-2. HDLC Formatter Logic Diagram
A-4
Send Message Control
Address Latch Enable
Transmit Clock Input
Receive Clock Input
Transmit Byte Input
Receive Data Input
Receive Data Input
Address-Data Bus
Send FCS Control
Initialization Input
Read Strobe
Write Strobe
Chip Select
Ground
Ground
Ground
Ground
Ground
VCC
I/O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
47–50, 53–56
This diagram pertains only to HDLC mode operation, for which some of the pins
are reassigned from CN8330 framer functions, i.e., the transmit data output
comes from a pin (RXCCK/TXNRZ) assigned to the receiver in CN8330 framer
operation.
Figure A-2 is a logic diagram showing the functional partitioning of the pins.
2–9
13
14
15
16
11
58
45
43
42
67
64
65
66
44
61
60
19
ALE
CS
RD*
WR*
AD[7:0]
TXCKI
CBITI
TDAT[7:0]
SNDFCS
SNDMSG
PPDLONLY
MON/MIC*
TESTI
INIT*
RXPOS
RXNEG
DS3CKI
RXCKI
FIFEN
I = Input, O = Output
Local Processor
Conexant
Control and
Transmitter
Receiver
Interface
Section
Section
Test
RDAT[7:0]
VALFCS
RXMSY
CNTINT
RXDAT
RXBCK
TXCCK
TXPOS
TXNEG
TXSYO
DS3/E3 Framer with 52 Mbps HDLC Controller
RXCLK
TXNRZ
TXBCK
TCLKO
TESTO
CBITO
DLINT
IDLE
VCO
62
63
57
46
40
39
59
18
41
20
21
22
37
38
34-22
24
25
12
23
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O No Connect
O
O
Receive Serial Data Output
No Connect
Receive Clock Output
No Connect
Transmit Data Output
Receive Byte Output
Receive Idle Status
Receive FCS Status
No Connect
Receive Byte Clock
Transmit Byte Clock
No Connect
No Connect
No Connect
No Connect
Transmit Clock Output
No Connect
No Connect
CN8330
100441E