CN8330EPD CONEXANT [Conexant Systems, Inc], CN8330EPD Datasheet - Page 19

• Manufacturer Part Number: CN8330EPD
• Description: DS3/E3 Framer with 52 Mbps HDLC Controller
• Manufacturer: CONEXANT [Conexant Systems, Inc]

CN8330
DS3/E3 Framer with 52 Mbps HDLC Controller
Table 1-2. Hardware Signal Definitions (2 of 5)
100441E
DLINT/SOURCELB
AD[7]/FRMERR
CNTINT/LINELB
AD[4]/IDLE
AD[5]/PAR
AD[6]/LCV
Pin Label
TESTO
TESTI
INIT*
Address-Data 4/Idle Code
Detection
Address-Data 5/Parity Error
Detection
Address-Data 6/Line Code
Violation
Address-Data 7/
Frame Bit Error
Counter Interrupt/
Line Loopback
Data Link Interrupt/Source
Loopback
Test In
Initialization
Test Out
Signal Name
Conexant
B/O
B/O
B/O
B/O
I/O
O/I
O/I
O
I
I
Part of the bidirectional 8-bit multiplexed
address-data bus when MON/MIC* is tied low. When
in stand-alone mode, this pin is an active-high
monitor output indicating an idle code detection.
Part of the bidirectional 8-bit multiplexed
address-data bus when MON/MIC* is tied low. When
in stand-alone mode, this pin is an active-high
monitor output indicating a parity error.
Part of the bidirectional 8-bit multiplexed
address-data bus when MON/MIC* is tied low. When
in stand-alone mode, this pin is an active-high
monitor output indicating a line code violation.
Part of the bidirectional 8-bit multiplexed
address-data bus when MON/MIC* is tied low. When
in stand-alone mode, this pin is an active-high
monitor output indicating a frame bit error.
The composite interrupt signal generated by the
error counters when MON/MIC* is tied low. When
MON/MIC* is tied high, this pin controls line
loopback transmission in stand-alone mode. CNTINT
is an active-low output; LINELB is an active-high
input.
The composite interrupt signal generated by the data
links when MON/MIC* is tied low. When MON/MIC*
is tied high, this pin controls source loopback
transmission in stand-alone mode. DLINT is an
active-low output; SOURCELB is an active-high
input.
Used for test functions only. Should be tied to
ground for normal operation.
Active low initialization control. Not all internal
storage elements are affected by this signal. See
Clock Interface and Initialization in the Overview
section of the Functional Description chapter.
Used for test functions only. Should be left
disconnected for normal operation.
Definition
1.0 Product Description
1.1 Pin Descriptions
(1)
(1)
(1)
(1)
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