CN8330EPD CONEXANT [Conexant Systems, Inc], CN8330EPD Datasheet - Page 18
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CN8330EPD
Manufacturer Part Number
CN8330EPD
Description
DS3/E3 Framer with 52 Mbps HDLC Controller
Manufacturer
CONEXANT [Conexant Systems, Inc]
Datasheet
1.CN8330EPD.pdf
(101 pages)
- Current page: 18 of 101
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1.0 Product Description
1.1 Pin Descriptions
Table 1-2. Hardware Signal Definitions (1 of 5)
1-8
WR*/CRC32
ALE/PAREN
RD*/ALM1
MON/MIC*
AD[0]/LOS
AD[1]/OOF
Pin Label
AD[3]/YEL
AD[2]/AIS
CS/ALM0
Address Latch
Enable/Parallel Input Enable
Chip Select/Alarm 0
Read/Alarm 1
Write/Cycle Redundancy
Check 32
Monitor/Microprocessor
Mode Select
Address-Data 0/Loss of
Signal
Address-Data 1/Out of Frame
Address-Data 2/Alarm
Indication Signal
Address-Data 3/Yellow Alarm
Detection
Signal Name
Conexant
B/O
B/O
B/O
B/O
I/O
I
I
I
I
I
A dual-purpose active-high signal which, when
MON/MIC* is tied low, is microprocessor-generated
and causes the CN8330 to latch in the address on
the address-data bus. When MON/MIC* is tied high
(stand-alone mode), the parallel input for the PPDL
formatter is enabled. When this pin is tied low,
transmit data is sourced from the serial input
TDAT[6]/TXDAT.
A dual-purpose signal that enables read/write
functions when MON/MIC* is tied low, and controls
AIS transmission in stand-alone mode when
MON/MIC* is tied high. Both CS and ALM0 are
active high signals.
A dual-purpose signal that enables read data to be
passed to the address-data bus when MON/MIC* is
tied low, and controls idle code transmission in
stand-alone mode when MON/MIC* is tied high,
RD* is an active low signal and ALM1 is
active-high.
A dual-purpose signal that latches write data from
the address-data bus when MON/MIC* is tied low,
and controls the Cycle Redundancy Check (CRC)
when MON/MIC* is tied high. WR* is an active low
signal. In stand-alone mode, a high-speed 32-bit
CRC calculation is enabled if CRC32 is high; if low, a
16-bit calculation is performed.
Selects either microprocessor mode when tied low,
or stand-alone monitor mode when tied high. The
state of MON/MIC* determines which function the
dual-purpose pins (AD[7:0]) serve. The standalone
mode is valid only in DS3 mode.
Part of the bidirectional 8-bit multiplexed
address-data bus when MON/MIC* is tied low. When
in stand-alone mode, this pin is an active-high
monitor output indicating loss of signal.
Part of the bidirectional 8-bit multiplexed
address-data bus when MON/MIC* is tied low. When
in stand-alone mode, this pin is an active-high
monitor output indicating an out-of-frame state.
Part of the bidirectional 8-bit multiplexed
address-data bus when MON/MIC* is tied low. When
in stand-alone mode, this pin is an active-high
monitor output indicating alarm indication signal
detection.
Part of the bidirectional 8-bit multiplexed
address-data bus when MON/MIC* is tied low. When
in stand-alone mode, this pin is an active-high
monitor output indicating a yellow alarm.
DS3/E3 Framer with 52 Mbps HDLC Controller
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Definition
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CN8330
100441E
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