CN8330EPD CONEXANT [Conexant Systems, Inc], CN8330EPD Datasheet - Page 20

• Manufacturer Part Number: CN8330EPD
• Description: DS3/E3 Framer with 52 Mbps HDLC Controller
• Manufacturer: CONEXANT [Conexant Systems, Inc]

1.0 Product Description
1.1 Pin Descriptions
Table 1-2. Hardware Signal Definitions (3 of 5)
1-10
TDAT[4]/LCVERRI
TXBCK/TXGAPCK
TDAT[5]/TXENCI
TDAT[6]/TXDATI
TXPOS, TXNEG
TDAT[7]/TXSYI
PPDLONLY
Pin Label
TDAT[3:0]
SNDMSG
SNDFCS
TCLKO
TXSYO
TXCCK
TXCKI
CBITI
Transmit Clock Out
Transmit Bipolar
Positive, Negative
Transmit Data Bits 3–0 (Bit 0
is the LSB)
Transmit Data Bit 4/Line
Code Violation Error In
Transmit Data Bit 5/Transmit
Encoder In
Transmit Data Bit 6/Transmit
Serial Data
Transmit Data Bit 7/Transmit
M-Sync In
Transmit M-Sync Out
Transmit Clock In
Transmit Byte Clock/Gapped
Clock
Send Message
Send Frame Check Sequence
Transmit C/N-Bit Serial In
Transmit C/N-Bit Clock
Payload Parallel Data Only
Select
Signal Name
Conexant
I/O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
Used to clock out the TXPOS and TXNEG outputs.
Data is clocked out on the rising edge of TCLKO.
The positive and negative pulses generated by the
B3ZS/HDB3 encoder.
In parallel mode
of the byte-oriented data that is input to the PPDL
transmitter in response to the transmit byte clock,
TXBCK.
In parallel mode, the TDAT[4] is bit 4 of the
byte-oriented data that is input to the PPDL
transmitter. In serial mode, LCVERRI allows test
equipment to insert LCVs into the transmit stream
under microprocessor control, in both DS3 and E3
modes.
In parallel mode, TDAT[5] is bit 5 of the
byte-oriented data that is input to the PPDL
transmitter. In serial mode, TXENCI is an alternate
direct input to the B3ZS/HDB3 encoder.
In parallel mode, TDAT[6] is bit 6 of the
byte-oriented data that is input to the PPDL
transmitter. In serial mode, TXDATI is applied to the
transmitter.
In parallel mode, TDAT[7] is the MSB (Bit 7)of the
byte-oriented data that is input to the PPDL
transmitter. In serial mode, TXSYI is applied to the
transmitter.
The transmit M-frame sync output.
TXCKI rising edge is used to sample parallel data,
while the falling edge is used to sample serial data.
In parallel mode, TXBCK clocks the byte-oriented
data that is input to the PPDL transmitter. In serial
mode, TXGAPCK is a transmit clock that is gapped
during overhead bit intervals in either E3 or DS3
modes.
In parallel mode, SNDMSG initiates message
transmission in the PPDL transmitter.
In parallel mode, SNDFCS initiates transmission of
the 16- or 32-bit frame check sequence on the PPDC
transmitter.
The serial C-bit (DS3 mode) or N-bit (E3 mode) data
input to be transmitted.
Used to sample the CBITI input on the falling edge of
TXCCK.
Enables the PPDL-only mode in which no DS3/E3
framing is inserted. This mode is entered by tying
this pin high.
DS3/E3 Framer with 52 Mbps HDLC Controller
(2)
, these bits form the lower nibble
Definition
CN8330
100441E