CN8380EPF CONEXANT [Conexant Systems, Inc], CN8380EPF Datasheet
CN8380EPF
Related parts for CN8380EPF
CN8380EPF Summary of contents
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Advance Information This document contains information on a product under development. The parametric information contains target parameters that are subject to change. CN8380 Quad T1/E1 Line Interface The CN8380 is a fully integrated quad line interface unit for both 1.544 ...
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... Ordering Information Model Number CN8380EPF CN8398EVM Revision History Revision A Information provided by Conexant Systems, Inc. (Conexant) is believed to be accurate and reliable. However, no responsibility is assumed by Conexant for its use, nor any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent rights of Conexant other than for circuitry embodied in Conexant products ...
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CN8398EVM Octal T1/E1 Evaluation Module CN8380 Quad T1/E1 LIU Microprocessor Control 8380_002 Contact a Conexant representative for EVM availability and price. Detailed Feature Summary Interface Compatibility • T1.102–1993 • G.703 at 1.544 or 2.048 Mbps • ITU-T Recommendation I.431 Receive ...
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N8380DSA Conexant Advance Information ...
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Table of Contents List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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CN8380 Quad T1/E1 Line Interface Per Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents viii Conexant Advance Information CN8380 Quad T1/E1 Line Interface N8380DSA ...
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CN8380 Quad T1/E1 Line Interface List of Figures Figure 1-1. CN8380 Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures x Conexant Advance Information CN8380 Quad T1/E1 Line Interface N8380DSA ...
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CN8380 Quad T1/E1 Line Interface List of Tables Table 1-1. Hardware Signal Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables xii Conexant Advance Information CN8380 Quad T1/E1 Line Interface N8380DSA ...
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Pin Descriptions The CN8380 is packaged in a 128-pin metric quad flat pack (MQFP). A pinout diagram is illustrated in and Figure are provided in The following input pins contain an internal pull-up resistor (> and ...
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Pin Descriptions Figure 1-1. CN8380 Pinout Diagram CLADI 1 VAACL 2 3 GNDCL REFCKI 4 VSS 5 VDD 6 CLK32 7 CLK1544 8 CLK2048 9 CLADO 10 VSS 11 VDD 12 RNEGO/BPV [4] 13 RPOSO/RDATO [4] 14 RCKO [4] ...
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CN8380 Quad T1/E1 Line Interface Figure 1-2. CN8380 Logic Diagram (Host Mode) Hardware/Host Mode HM Hardware/Host Mode Hardware Reset I RESET Hardware Reset I Local Loopback I LLOOP[1:4] Local Loopback I Remote Loopback I RLOOP[1:4] Remote Loopback I Serial Data ...
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Pin Descriptions Figure 1-3. CN8380 Logic Diagram (Hardware Mode) VDD Hardware/Host Mode Hardware Reset I Jitter Attenuator Path I Jitter Attenuator Size I Unipolar/Bipolar I Transmitter Termination I Transmit Pulse Template I Clock Polarity I Raw Mode Select I ...
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CN8380 Quad T1/E1 Line Interface Table 1-1. Hardware Signal Definitions ( Pin Label Signal Name RPOSO[1:4] RX Positive Rail (Bipolar Mode) RDATO[1:4] RX Data (Unipolar Mode) RNEGO[1:4] RX Negative Rail (Bipolar Mode) BPV[1:4] Bipolar Violation (Unipolar Mode) RCKO[1:4] ...
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Pin Descriptions Table 1-1. Hardware Signal Definitions ( Pin Label Signal Name XTIP[1:4] Transmit Tip XRING[1:4] Transmit Ring CLADI CLAD Input REFCKI Reference Clock CLK32 32 MHz Clock Output CLK1544 T1 Clock Output CLK2048 E1 Clock Output ...
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CN8380 Quad T1/E1 Line Interface Table 1-1. Hardware Signal Definitions ( Pin Label Signal Name RESET Hardware Reset UNIPOLAR Unipolar Mode Select ZCS Zero Code Suppression Select CLK_POL Rx Clock Polarity Select PTS(2:0) Transmit Pulse Template Select HTERM ...
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Pin Descriptions Table 1-1. Hardware Signal Definitions ( Pin Label Signal Name RLOS [1:4] Receive Loss of Signal LLOOP [1:4] Local Loop RLOOP [1:4] Remote Loop TDO Test Data Output TDI Test Data Input TMS Test Mode ...
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CN8380 Quad T1/E1 Line Interface Table 1-1. Hardware Signal Definitions ( Pin Label Signal Name VAACL CLAD Supply GNDCL Ground VDD Digital Supply VSS Ground VGG ESD Rail N.C. No Connect NOTE(S): 1. I/O Types Standard ...
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Pin Descriptions 1-10 Conexant Advance Information CN8380 Quad T1/E1 Line Interface N8380DSA ...
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Circuit Description 2.1 Overview The CN8380 includes four identical T1/E1 transceiver channels and a common CLAD packaged in a 128-pin MQFP carrier designed to interface T1/E1 framers operate as a stand-alone line interface for synchronous ...
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Circuit Description 2.1 Overview Figure 2-1. Detailed Block Diagram 2-2 Conexant Advance Information CN8380 Quad T1/E1 Line Interface N8380DSA ...
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CN8380 Quad T1/E1 Line Interface 2.2 Configuration and Control 2.2.1 Hardware Mode In Hardware Mode, the device is controlled using dedicated hardware control pins. In this mode, the four channels are configured globally to identical operating modes (T1, E1, transmit ...
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Circuit Description 2.2 Configuration and Control Figure 2-2. Host Serial Port Signals CS SCLK R/W SDI A0 A1 Address/Control Byte SDO CS SCLK SDI R Address/Control Byte SDO 8380_007 2.2.4 Reset The CN8380 supports three reset methods: ...
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CN8380 Quad T1/E1 Line Interface CLK1544, CLK2048, and CLADO clock outputs are enabled. Transmitter clocks, TCLK[1:4], are configured as inputs. The by DPM). 2.2.4.1 Power-on Reset An internal power-on reset process is initiated during power-up. When VDD has reached approximately ...
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Circuit Description 2.3 Receiver 2.3 Receiver Bipolar AMI pulses are input on the receiver input pins, RTIP[n] and RRING[n]. The receiver recovers clock and data from the AMI signal which has been attenuated and distorted due to the line ...
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CN8380 Quad T1/E1 Line Interface 2.3.1.1 Raw Receive Optionally, the data slicer outputs, before re-timing, can be routed directly to the Mode RPOSO and RNEGO digital output pins. This option (raw receive mode) is selected by asserting the RAWMD register ...
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Circuit Description 2.3 Receiver 2.3.1.4 Loss Of Signal The Receive Loss of Signal (RLOS) Detector monitors both consecutive 0s and Detector signal level. Receive Analog Loss Of Signal (RALOS) is declared when RTIP/RRING input signal amplitude is a certain ...
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CN8380 Quad T1/E1 Line Interface path, RCKO is replaced with the jitter attenuated clock. The JAT performance is discussed in In Host Mode, the JAT is configured for each channel independently and is put in the receive path by setting ...
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Circuit Description 2.4 Transmitter 2.4 Transmitter Bipolar or unipolar, NRZ digital transmit data are input on TPOSI and TNEGI using the transmit clock TCLK. Data are converted into AMI pulses, shaped according to required standards, and transmitted to the ...
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CN8380 Quad T1/E1 Line Interface enabled per channel by writing register bit UNIPOLAR [RLIU_CR; addr n1]. 2.4.1.2 Unipolar Mode In unipolar mode, TPOSI is replaced with TDATI and accepts unipolar NRZ- formatted transmit data. TNEGI is not ...
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Circuit Description 2.4 Transmitter In Hardware Mode, AIS can be controlled only manually by pulling the [n] hardware pin low. If TCLK[n] is present, then it is used to transmit AIS. TAIS If TCLK[n] is not present (for two ...
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CN8380 Quad T1/E1 Line Interface 2.4.5 Pulse Shaper All transmit pulse shaping to meet E1 and T1 transmission standards is done internally, eliminating the need for external shaping circuitry. The pulse shape block receives bipolar NRZ transmit data, produces a ...
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Circuit Description 2.4 Transmitter In Host Mode, standard pulse templates are selected per channel by writing to register bits PULSE(2:0) [TLIU_CR; addr n2]. If desired, custom pulse shapes can be programmed for each channel using the SHAPEn [addr n8 ...
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CN8380 Quad T1/E1 Line Interface The standard transformer recommended has a turns ratio of 1:2. This turns ratio is required if parallel termination (Rt) or series resistors (Rs) are desired. The alternate transformer has a turns ratio of 1:1.36. This ...
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Circuit Description 2.4 Transmitter Option A Option A uses the standard 1:2 transformer, no series protection resistors (Rs), and no parallel termination (Rt) for T1 applications applications included because it is usually required to provide ...
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CN8380 Quad T1/E1 Line Interface Option C Option C uses the standard 1:2 transformer and no parallel termination (Rt) for T1 applications applications included because it is usually required to provide a minimal level of line ...
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Circuit Description 2.4 Transmitter Option E Option E uses the alternate 1:1.36 transformer, no series protection resistors (Rs), and no parallel termination (Rt) for T1 applications applications included because it is usually required to provide ...
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CN8380 Quad T1/E1 Line Interface 2.4.7 Transmitter Output Monitoring 2.4.7.1 Short Circuit The transmitter output pulse is monitored and a short circuit is detected when the Detect amplitude falls below an internally determined threshold for approximately 64-bit times. The short ...
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Circuit Description 2.5 Loopbacks 2.5 Loopbacks Three per-channel loopbacks are provided for system diagnostic testing: Local Analog Loopback, Local Digital Loopback, and Remote Line Loopback. Loopbacks can be controlled by either hardware pins or internal register bits. For hardware ...
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CN8380 Quad T1/E1 Line Interface 2.5.3 Remote Line Loopback Remote Line Loopback (RLL) causes the received data on RTIP/RRING line inputs to be looped back and re-transmitted on XTIP/XRING line outputs. This loopback includes all receive and transmit circuitry and ...
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Circuit Description 2.6 Jitter Attenuator 2.6 Jitter Attenuator The jitter attenuator (JAT) attenuates jitter in the receive or transmit path, but not both simultaneously. The JAT path configuration and elastic store depth is controlled by the JDIR and JSEL(2:0) ...
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CN8380 Quad T1/E1 Line Interface Figure 2-8. Receiver Input Jitter Tolerance 10000 1000 Typical Receiver Tolerance with Various JAT Sizes Selected 138 UI 100 TR 62411 (T1) Minimum Tolerance 10 G.824 (T1) Minimum Tolerance Rec. G.823 (E1) Minimum Tolerance 1 ...
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Circuit Description 2.6 Jitter Attenuator Figure 2-9. Typical JAT Transfer Characteristics with Various JAT Sizes 0 -10 -20 -30 -40 PUB 62411 -50 (Max. Atten. Boundary) - 2-24 Rec G.735 (Min. Atten Boundary) (Min. Atten. Boundary) JAT ...
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CN8380 Quad T1/E1 Line Interface 2.7 Clock Rate Adapter The CLAD uses an input clock reference at a particular frequency (8 kHz to 16,384 kHz) to synthesize output clocks at a different frequency (8 kHz to 16,384 kHz). The CLAD ...
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Circuit Description 2.7 Clock Rate Adapter 2.7.1 Inputs In Hardware Mode, the CLAD input timing reference is normally taken from a line rate (1,544 kHz—T1 or 2,048 kHz—E1) clock on the CLADI pin. The line rate is determined globally ...
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CN8380 Quad T1/E1 Line Interface Table 2-11. CLAD Reference Frequencies and Configuration Examples ( CLAD Reference (kHz 128 256 512 1024 2048 4096 8192 16,384 32,768 12.0625 24.125 48.25 96.5 193 386 772 1544 3088 ...
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Circuit Description 2.7 Clock Rate Adapter Table 2-11. CLAD Reference Frequencies and Configuration Examples ( CLAD Reference (kHz) 384 768 1536 160 320 640 1280 2560 To configure the CLAD ...
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CN8380 Quad T1/E1 Line Interface 2.8 Test Access Port (JTAG) The CN8380 incorporates printed circuit board testability circuits in compliance with IEEE Std P1149.1a–1993, IEEE Standard Test Access Port and Boundary–Scan Architecture, commonly known as JTAG (Joint Test Action Group). ...
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Circuit Description 2.8 Test Access Port (JTAG) 2-30 Conexant Advance Information CN8380 Quad T1/E1 Line Interface N8380DSA ...
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Registers 3.1 Address Map The address map in Table 3-1 lists the three types of registers: • Global Control and Status Registers • Per Channel Registers • Transmitter Shape Registers Table 3-1. Address Map ( Address ...
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Registers 3.1 Address Map Table 3-1. Address Map ( Address (Hex) Acronym nA SHAPE2 nB SHAPE3 nC SHAPE4 nD SHAPE5 nE SHAPE6 nF SHAPE7 05 CTEST 07 FREG 08 TESTA1 09 TESTA2 0A FUSE_CH1 0B FUSE_CH2 0C ...
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CN8380 Quad T1/E1 Line Interface 3.2 Global Control and Status Registers 00—Device Identification (DID DID[7] DID[6] DID[5] Device ID DID[7:4] Device Revision DID[3:0] 01—Global Configuration (GCR RESET G_T1/E1N CLK_OE Global Reset When written to ...
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Registers 3.2 Global Control and Status Registers CLAD Multiplexer Select CMUX[2:0] phase detector if FREE = 0 [CLAD_CR; addr 02]. The source can be the receive recovered clock output (RCKO) from any of the four channels or the CLAD ...
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CN8380 Quad T1/E1 Line Interface 03—CLAD Frequency Select (CSEL VSEL[3] VSEL[2] VSEL[1] CLADV Frequency Select—Applicable only if FREE [CLAD_CR; addr 02 Picks one of VSEL[3:0] 13 CLAD divider chain frequencies to feed back to the ...
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Registers 3.2 Global Control and Status Registers CLADO Frequency Select OSEL[3:0] CLADO pin. OSEL 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 04—CLAD Phase Detector Scale Factor (CPHASE ...
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CN8380 Quad T1/E1 Line Interface 05—CLAD Test (CTEST CTEST[7] CTEST[6] CTEST[5] Factory use only. Must be remain at default value, 00. 06—CLAD Status (CSTAT — — — CLAD Phase Detector Error CPDERR CPDERR indicates ...
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Registers 3.2 Global Control and Status Registers 0A—(FUSE_CH1 — — F_TR[5] Factory use only. Must be remain at default value, 00. 0B—(FUSE_CH2 — — — Factory use only. Must be remain at default ...
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CN8380 Quad T1/E1 Line Interface 0F—(TESTD D_CTL[2] D_CTL[1] D_CTL[0] Factory use only. Must be remain at default value, 00. N8380DSA 4/21/99 3.2 Global Control and Status Registers D_CH[1] D_CH[0] D_MD[2] Conexant Advance Information 3.0 ...
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Registers 3.3 Per Channel Registers 3.3 Per Channel Registers 10, 20, 30, 40—Jitter Attenuator Configuration (JAT_CR — T1/E1 JEN T1/E1 Select — Enables receive and transmit circuits to operate at either the line ...
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CN8380 Quad T1/E1 Line Interface 11, 21, 31, 41—Receiver Configuration (RLIU_CR UNIPOLAR ZCS CLK_POL Unipolar Mode — Selects between unipolar and bipolar modes for digital transmit and receive UNIPOLAR signals. In unipolar mode, RPOSO/RNEGO signals are replaced ...
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Registers 3.3 Per Channel Registers Enable Receive Signal Squelch SQUELCH zero when RALOS is declared. SQUELCH is useful in attached framer applications to allow the framer to detect LOS during an RALOS condition Normal 1 = Squelch ...
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CN8380 Quad T1/E1 Line Interface Transmit Pulse Template Select PULSE[2:0] shaped to meet the transmit pulse template according to the selected cable length and type. Custom shape programming for alternative cable types or pulse templates can be set using the ...
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Registers 3.3 Per Channel Registers AIS transmission does not affect transmit data that is looped back to the receiver during Local Digital Loopback. This allows Local Digital Loopback to be active simultaneously with the transmission of AIS. If TAIS ...
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CN8380 Quad T1/E1 Line Interface LLOOP Pin Enable—Allows the use of the LLOOP hardware pin instead of the LLOOP LLOOP_PE register bit to control loopbacks Use LLOOP register bit 1 = Use LLOOP pin RLOOP Pin Enable—Allows the ...
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Registers 3.3 Per Channel Registers 16, 26, 36, 46—Interrupt Status Register (ISR) An Interrupt Status register (ISR) bit is latched active (high) whenever its corresponding interrupt source [ALARM; addr n5] reports an interrupt event. All latched ISR bits are ...
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CN8380 Quad T1/E1 Line Interface 3.4 Transmitter Shape Registers The following SHAPE registers allow custom programming of the transmit signal pulse shapes. Each set of eight registers determines the shape for its corresponding channel. A channel [n] is configured to ...
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Registers 3.4 Transmitter Shape Registers 51—(TESTA4 A_TEST[31] A_TEST[30] A_TEST[29] Factory use only. Must be remain at default value, 00. 3- A_TEST[28] A_TEST[17] A_TEST[16] Conexant Advance Information CN8380 Quad T1/E1 Line Interface R/W 1 ...
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Electrical/Mechanical Specifications This chapter contains the following sections: • Absolute Maximum Ratings • Recommended Operating Conditions • DC Characteristics • Performance Characteristics • • Packaging 4.1 Absolute Maximum Ratings Table 4-1. Absolute Maximum Ratings Symbol V Power Supply (measured ...
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Electrical/Mechanical Specifications 4.2 Recommended Operating Conditions 4.2 Recommended Operating Conditions Table 4-2. Recommended Operating Conditions Symbol Supply voltage DD, AA, AAT AAR, AACC ESD Rail ( Ambient operating temperature amb (1) ...
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CN8380 Quad T1/E1 Line Interface 4.3 DC Characteristics Table 4-3. DC Characteristics Symbol Parameter I Supply current (all channels in low power DD mode, PDN [TLIU_CR; addr n2]) Supply current (50% 1s, all channels enabled, includes transmit load current) Supply ...
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Electrical/Mechanical Specifications 4.4 Performance Characteristics 4.4 Performance Characteristics Table 4-4. Performance Characteristics Parameter T1 receiver sensitivity (attenuation @ 772 kHz) E1 receiver sensitivity (attenuation @ 1024 kHz) RTIP[n]. RRING[n] inputs: Input impedance (unterminated) Peak-to-peak voltage (differential) Return loss Receive ...
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CN8380 Quad T1/E1 Line Interface 4.5 AC Characteristics This section provides details about the following timing features: • XOE • RESET • CLAD • Receiver signals • Transmitter signals • Host serial port • JTAG interface Table 4-5. XOE Timing ...
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Electrical/Mechanical Specifications 4.5 AC Characteristics Table 4-6. RESET Timing Parameters Symbol Parameter 1 RESET pulse width 2 RESET low to output signals three-state 3 RESET[n] high to output signals active NOTE(S): 1. Output signals: RCKO[n], RPOSO[n], RNEGO[n], XTIP[n], XRING[n], ...
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CN8380 Quad T1/E1 Line Interface Table 4-7. CLAD Timing Parameters Symbol Parameter 1 REFCKI frequency — CLADI frequency 2 Duty cycle REFCKI, CLADI 3 Rise/fall time (10% to 90%) REFCKI, CLADI 1 CLADO frequency 1 CLK32 frequency 1 CLK1544 frequency ...
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Electrical/Mechanical Specifications 4.5 AC Characteristics Table 4-8. Receiver Signals Timing Parameters Symbol Parameter 1 RCKO[n] frequency 2/1 RCKO[n] duty cycle — Rise/fall time (10% to 90%) RCKO[n], RPOSO[n], RNEGO[n], RDATO[n], BPV[n] 3 RCKO[n] (rising or falling edge) to data ...
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CN8380 Quad T1/E1 Line Interface Table 4-9. Transmitter Signals Timing Parameters Symbol Parameter 1 TCLK[n] frequency (input or output) 2/1 TCLK[n] duty cycle (input) 2/1 TCLK[n] duty cycle (output) — Rise/fall time (10% to 90%) TCLK[n], TPOSI[n], TNEGI[n], TDATI[n] 3 ...
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Electrical/Mechanical Specifications 4.5 AC Characteristics Table 4-10. Host Serial Port Timing Parameters Symbol Parameter 1 CS Setup Before SCLK Rising Edge 2, 3 SCLK Frequency 2 SCLK High Pulse Width 3 SCLK Low Pulse Width 4 SDI to SCLK ...
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CN8380 Quad T1/E1 Line Interface Figure 4-7. Host Serial Port Write Timing SCLK 4 5 SDI 0 Address/Command 8380_022 Figure 4-8. Host Serial Port Read Timing SCLK 4 5 SDI 1 Address/Command SDO 8380_023 ...
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Electrical/Mechanical Specifications 4.5 AC Characteristics Table 4-11. JTAG Interface Timing Parameters Symbol Parameter 1 TCK pulse width high 2 TCK pulse width low 3 TMS, TDI setup to TCK rising edge 4 TMS, TDI hold after TCK high 5 ...
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CN8380 Quad T1/E1 Line Interface 4.6 Packaging Figure 4-10. 128-Pin MQFP Mechanical Drawing PIN 1 REF DETAIL A 8380_027 N8380DSA 4.0 Electrical/Mechanical Specifications 2.00 ...
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Electrical/Mechanical Specifications 4.6 Packaging 4-14 Conexant Advance Information CN8380 Quad T1/E1 Line Interface N8380DSA ...
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Appendix A: Applicable Standards Table A-1. Applicable Standards ( Standard T1.101-1987 Digital Hierarchy—Timing Synchronization T1.102-1993 Digital Hierarchy—Electrical Interfaces T1.403-1995 Network to Customer Installation—DS1 Metallic Interface T1.408-1990 ISDN Primary Rate—Customer Installation Metallic Interfaces TR 41449-1986 ISDN Primary Rate Interface ...
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Appendix A : Applicable Standards Table A-1. Applicable Standards ( Standard Recommendation G.703 (1991) Physical/Electrical Characteristics of Hierarchical Digital Interfaces Recommendation G.704 (1991) Synchronous Frame Structures used at Primary Hierarchical Levels Recommendation G.706 (1991) Frame Alignment and CRC ...
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Appendix B: External Component Table B-1 oscillator specifications. Table B-1. Transformer Specifications Turns Ratio Pulse Engineering Part Number: Temp. 0 ° °C Octal SMT Serial Resistance Primary Inductance Isolation Voltage Leakage Inductance Note(s): (1) Contact Pulse Engineering for ...
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B Figure B-1. Minimum Hardware Configuration Hardware Mode Host Mode Channel 1 Digital CN8394 Quad T1/E1 Framer Channel 2 Digital Interface Channel 3 Digital Interface Channel 4 Digital Interface Oscillator Note(s): (1) Optional programmable receive termination: 75/100/120 (2) Required fixed ...
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Appendix C: Acronym List Acronym AGC AIS AMI ANSI B8ZS BABT BPV BSDL CCIR CIF CLAD CMOS CRC CSU DAC DMA DPM DSX ETSI FCC FIFO GPIO HDB3 HDSL ISDN ITU–T JAT JTAG LAL N8380DSA 4/21/99 C ...
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Appendix C : Acronym List LDL LIU LOS MSB NCO NCTE NRZ PCI PCM PLL MQFP PRBS PRI RALOS RLL RLOS RPLL RZCS SDH SONET TAP TLOC TLOS TZCS UI UTP ZCS C-2 local digital loopback line interface unit loss ...
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Further Information Hong Kong literature@conexant.com Phone: (852) 2827 0181 1-800-854-8099 (North America) Fax: (852) 2827 6488 33-14-906-3980 (International) India Phone: (91 11) 692 4780 Web Site www.conexant.com Fax: (91 11) 692 4712 World Headquarters Korea Phone: (82 2) 565 2880 ...