CN8330EPD CONEXANT [Conexant Systems, Inc], CN8330EPD Datasheet - Page 89

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CN8330EPD

Manufacturer Part Number
CN8330EPD
Description
DS3/E3 Framer with 52 Mbps HDLC Controller
Manufacturer
CONEXANT [Conexant Systems, Inc]
Datasheet
CN8330
DS3/E3 Framer with 52 Mbps HDLC Controller
Figure A-3. HDLC Formatter Logic Diagram - 80-Pin MQFP
100441E
Send Message Control
Address Latch Enable
Transmit Clock Input
Receive Clock Input
Transmit Byte Input
Receive Data Input
Receive Data Input
Address-Data Bus
Send FCS Control
Initialization Input
Read Strobe
Write Strobe
Chip Select
Ground
Ground
Ground
Ground
Ground
VCC
I/O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
44-47, 51-54
73-80
56
42
39
38
5
6
7
8
3
69
66
67
68
41
63
58
11
TXCKI
CBITI
TDAT[7:0]
SNDFCS
SNDMSG
ALE
CS
RD*
WR*
AD[7:0]
PPDLONLY
MON/MIC*
TESTI
INIT*
RXPOS
RXNEG
DS3CKI
RXCKI
FIFEN
I = Input, O = Output
Local Processor
Control and
Transmitter
Receiver
Interface
Section
Section
Conexant
Test
RDAT[7:0]
VALFCS
RXMSY
CNTINT
RXDAT
RXBCK
TXCCK
TXPOS
TXNEG
TXSYO
RXCLK
TXNRZ
TXBCK
TCLKO
TESTO
CBITO
DLINT
IDLE
VCO
64
65
55
43
36
35
57
10
37
12
13
14
33
34
22-29
16
17
4
15
Appendix A Multimegabit HDLC Formatter
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O No Connect
O
O
Receive Serial Data Output
No Connect
Receive Clock Output
No Connect
Transmit Data Output
Receive Byte Output
Receive Idle Status
Receive FCS Status
No Connect
Receive Byte Clock
Transmit Byte Clock
No Connect
No Connect
No Connect
No Connect
Transmit Clock Output
No Connect
No Connect
A.2 Block and Logic Diagrams
A-5

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