CN8330EPD CONEXANT [Conexant Systems, Inc], CN8330EPD Datasheet - Page 77
CN8330EPD
Manufacturer Part Number
CN8330EPD
Description
DS3/E3 Framer with 52 Mbps HDLC Controller
Manufacturer
CONEXANT [Conexant Systems, Inc]
Datasheet
1.CN8330EPD.pdf
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CN8330
DS3/E3 Framer with 52 Mbps HDLC Controller
Table 4-2. Clock Timing Requirements
Figure 4-2. Output and Input Signal Timing
100441E
Low Pulse Width -
High Pulse Width -
Cycle Time - t
Cycle Time
Low Pulse Width
High Pulse Width
Timing Requirements
Output
Signal
Clock
cyc
wl
wh
t pd
RXCKI, DS3CKI, TXCKI
RXCKI, DS3CKI, TXCKI
RXCKI, DS3CKI, TXCKI
—
RXBCK
RXBCK
relationships for all output and input signals. Propagation delays for the output
signals are listed below. The output signal timings are relative to the listed edge of
the clock. Clock outputs derived from clock inputs are listed with the edge as
both. This means that the delay number given applies for either edge. Input
signals should have setup and hold times with respect to the listed edge of the
given input clock. All times are listed in nanoseconds and are measured with
30 pF loading on the output pins.
Figure 4-2
Clock
and
Tables 4-2
Conexant
Signal
Clock
6 RXCKI
2 RXCKI
p wl
Input
Input
Min.
19.0
5.0
5.0
—
through
t su
(44.736 MHz)
Table 4-4
p wh
t hd
Typical
11.2
11.2
22.4
—
—
4.0 Mechanical/Electrical Specifications
illustrate the clock and data
8 RXCKI
(34.368 MHz)
Typical
14.55
14.55
29.1
4.1 Timing Requirements
—
—
Units
ns
ns
ns
ns
ns
ns
4-3
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