CN8330EPD CONEXANT [Conexant Systems, Inc], CN8330EPD Datasheet - Page 45

• Manufacturer Part Number: CN8330EPD
• Description: DS3/E3 Framer with 52 Mbps HDLC Controller
• Manufacturer: CONEXANT [Conexant Systems, Inc]

CN8330
DS3/E3 Framer with 52 Mbps HDLC Controller
2.4.3 Received Signal Output
Figure 2-11. Receiver Timing for Serial DS3 Mode
100441E
RXGAPCK
RDAT[6]/
RXBCK/
RXMSY
RXOVH
RXDAT
RXCLK
F4
The received unipolar signal is recovered and provided with a clock on RXDAT
and RXCLK. An M-frame synchronization signal and gapped clock are also
provided.
propagation delays for the DS3 receiver output signals. Refer to the Electrical and
Mechanical Specifications section for actual propagation delay specifications.
RXMSY is low during subframe 7 preceding the X1 bit in the first subframe.
Outputs change on the rising edge of the receive clock except for the gapped
clock on RXBCK/RXGAPCK. This clock is an inverted version of RXCLK with
a gapped pulse every 85 bits. The receive clock will be nominally 44.736 MHz.
Data on RXDAT can be clocked into the user's circuit with the rising edge of the
RXBCK/RXGAPCK if it is desired to observe only data bits (there is no rising
edge present during the overhead bit positions). The rising edge of RXBCK will
be mid-bit for each payload bit in the serial stream. An overhead indicator
RDAT[6]/RXOVH is available when the PPDL is not enabled. This signal is low
for each bit position that is an overhead bit in the receive serial stream.
84 Info Bits
Subframe 7
Figure 2-11
Conexant
shows a timing diagram for DS3 mode with negligible
X1
Subframe 1
84 Info Bits
2.0 Functional Description
2.4 Receiver Operation
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