CN8330EPD CONEXANT [Conexant Systems, Inc], CN8330EPD Datasheet - Page 46

• Manufacturer Part Number: CN8330EPD
• Description: DS3/E3 Framer with 52 Mbps HDLC Controller
• Manufacturer: CONEXANT [Conexant Systems, Inc]

2.0 Functional Description
2.4 Receiver Operation
Figure 2-12. Receiver Timing for Parallel DS3 Mode
Figure 2-13. E3 Receiver Output Timing
2-24
RXGAPCK
RDAT[7:0]
RXBCK/
RXMSY
RXCLK
RXGAPCK
RDAT[6]/
RXBCK/
RXOVH
RXMSY
RXCLK
RXDAT
data
Subframe 7
1520/1524 Info Bits
mode is enabled by setting the ParaEn bit in the Feature Control Register and
setting the DisPPDL bit in the PPDL Control Register. The receive data is valid
on either the rising or falling edge of RXBCK.
the PPDL enabled. The clock and data edge relationships are similar to those in
DS3 mode. The M-frame synchronization signal RXMSY is high during the
12-bit block corresponding to the 10-bit FAS and the A and N bits. If the PPDL is
enabled, the M-frame synchronization signal will be high for four additional bit
periods corresponding to the 1100 pattern found in SMDS formatted signals.
RDAT[6]/RXOVH will be low for 12 bits in serial mode and for 16 bits if the
PPDL is enabled.
Figure 2-12
Figure 2-13
data
illustrates the receiver timing for the parallel DS3 mode. This
illustrates a timing diagram for the E3 receiver output signal with
Conexant
Low for 12 or 16 Bits
High for 12 or 16 Bits
10-Bit FAS
data
Subframe 1
DS3/E3 Framer with 52 Mbps HDLC Controller
A/N/1100
data
Info Bits
data
CN8330
100441E