CN8330EPD CONEXANT [Conexant Systems, Inc], CN8330EPD Datasheet - Page 92
CN8330EPD
Manufacturer Part Number
CN8330EPD
Description
DS3/E3 Framer with 52 Mbps HDLC Controller
Manufacturer
CONEXANT [Conexant Systems, Inc]
Datasheet
1.CN8330EPD.pdf
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Appendix A Multimegabit HDLC Formatter
A.3 PPDL Transmitter
A-8
packet received, a packet received with a bad FCS, and an aborted packet. Each
packet is shown with one idle flag marking the end of the packet and the start of
the next packet. However, more than one flag can occur in the serial stream. The
output data will contain each occurrence of idle or abort flags with a pulse on
RXBCK.
receive serial clock input on DS3CKI and is present continuously like the transmit
byte clock. Nominally there will be one pulse on RXBCK for every eight clock
cycles on the receive serial clock. When an inserted transparency bit must be
deleted, the RXBCK period will be lengthened by one serial clock cycle. RXBCK
is present during the reception of FCS octets and idle flags. On a received
message with a valid 16-bit FCS, the last 2 byte clocks prior to IDLE and
VALFCS going high will be the received FCS octets that were appended to the
end of the message by the transmitter. In 32-bit mode, the last four received octets
will be FCS octets. The RDAT[7:0], IDLE, and VALFCS outputs are valid at least
one serial clock cycle period before the rising edge of RXBCK and are valid for at
least two serial clock cycle periods after the falling edge of RXBCK.
setting the LimitFCS control bit. In this mode, the FCS is checked only on the
first N bytes received after the opening flag and then held until the end of the
message. The locally calculated FCS is then compared to the last 2/4 bytes in the
message to determine if a valid FCS was received. The desired number N can be
from 1 to 16 (a value of 0 gives N=16) and is loaded in the FCSCnt control field.
This allows FCS checking only on the header information in a T1 packet voice
format.
Timing for this operation is shown in
The receive byte clock RXBCK is generated from the falling edge of the
FCS checking can be limited to the first N bytes of the received message by
Conexant
DS3/E3 Framer with 52 Mbps HDLC Controller
Figure
A-5. Shown are cases of a good
CN8330
100441E
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