CN8330EPD CONEXANT [Conexant Systems, Inc], CN8330EPD Datasheet - Page 27
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CN8330EPD
Manufacturer Part Number
CN8330EPD
Description
DS3/E3 Framer with 52 Mbps HDLC Controller
Manufacturer
CONEXANT [Conexant Systems, Inc]
Datasheet
1.CN8330EPD.pdf
(101 pages)
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CN8330
DS3/E3 Framer with 52 Mbps HDLC Controller
2.2.1 Transmitter Line Interface
100441E
2.2 Line Interfaces
The transmitted line signals are shown in
output sequence are shown. Separate signal pins provide the appropriate output
signal for positive and negative pulses. The outputs are a full clock period wide
and change on positive clock transitions of the TCLKO pin. For additional
information on the TXPOS and TXNEG outputs refer to Transmitter Outputs in
the Transmitter Operation section in this chapter
however, this encoding can be disabled to send AMI data without any zero code
suppression. Transmit NRZ data, prior to B3ZS/HDB3 encoding, is also available
on the RDAT[7]/TXNRZ pin when parallel mode is not selected and on the
RXCCK/TXNRZ pin when PPDLONLY mode is selected.
Figure 2-2. Transmitter Line Driver Outputs
TXNEG
TCLKO
TXPOS
B3ZS/HDB3 encoding is performed automatically on the output data stream;
Conexant
Figure
2-2. Nine bits of a representative
2.0 Functional Description
2.2 Line Interfaces
2-5
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