ZL30226/GA ZARLINK [Zarlink Semiconductor Inc], ZL30226/GA Datasheet - Page 94

• Manufacturer Part Number: ZL30226/GA
• Description: 4/8/16 Port IMA/TC PHY Device for xDSL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Synchronized access
Reset Value (Bin:
15:12
Bit #
11:8
Bit #
15:8
7:4
3:0
4:3
7
6
5
2
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
Unused. Read all 0’s.
Defines the integration period for an IMA Group n+4
1111: Reserved. Do not use.
1110: 2
1101: 2
...
0001: 2
0000: 2
Reserved. Write all 0’s.
Defines the integration period for an IMA Group N
1111: Reserved. Do not use.
1110: 2
1101: 2
1100: 2
1011: 2
1010: 2
1001: 2
1000: 2
0111: 2
0110: 2
0101: 2
0100: 2
0011: 2
0010: 2
0001: 2
0000: 2
Unused. Read all 0’s.
Upon a write to this register, the bit will go to 0 and will return to 1 when the transfer is
completed.
Toggle Bit. Changes its state after each rising edge of the bit 7 (ready bit).
Write 0 to initiate a transfer from the ZL30226/7/8 registers to the external RAM.
Write 1 to initiate a transfer from the external RAM to the ZL30226/7/8 registers.
Unused. Read all 0’s.
Reserved. Write 0 for normal operation.
0x0219 - 0x021C (4 reg)
1 register per 2 IMA groups. IMA Group 0 is paired with IMA group 4 and so on.
For ZL30226 groups 0, 1, 2 and 3 are used.
0C0C
0x0280
000000001X000000
Table 58 - RX External SRAM Access Control Register
22
22
15
21
21
20
19
14
11
09
08
18
17
16
13
12
10
09
08
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles (preferred value for SHDSL E1 service)
clock cycles (preferred value for SHDSL T1 service)
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles
Table 57 - RX IDCR Integration Registers
(1 reg)
Zarlink Semiconductor Inc.
ZL30226/7/8
94
Description
Description
Data Sheet