ZL30226/GA ZARLINK [Zarlink Semiconductor Inc], ZL30226/GA Datasheet - Page 23

• Manufacturer Part Number: ZL30226/GA
• Description: 4/8/16 Port IMA/TC PHY Device for xDSL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

ZL30227 Pin Description (continued)
B18,D18,C18,
B17,C17,A18,
AC16,AE16,
AF16,AC15,
AE15,AF15,
AD14,AE14
AA3,AA4,
AB2,AB1
A19,B19
AA1,Y3
Pin #
AF13
AF14
AC1
D16
C19
A17
A4
D7
A5
B6
C6
RXRingSync
TXRingSync O TDM Ring TX Sync. Synchronization output signal used to retrieve data and
RXRingData
TXRingData
RXRingClk
TXRingClk
LatchClk
PLLREF
REFCK
Name
Reset
TMS
TDO
TCK
[1:0]
[3:0]
[7:0]
[7:0]
TDI
Clk
I/O
O Output reference to an external PLL.
O TDM Ring TX Clock. Clock output signal used to align the TXRingSync and
O TDM Ring TX Data[7:0]. Data Bus connecting the TX TDM Ring port to the RX
O JTAG Test Data Output. Note: TDO is tristated by TRST pin.
I
I
I
I
I
I
I
I
I
I
Input Reference Clock inputs 3 to 0. Receive the de-jittered transmit clock
reference to be internally routed to the TXCKio transmit clocks. These pins
have internal weak pull-downs.
TXRingData. Should be connected to the RXRingClk input of the next ZL30227
device in the Ring. This output is in High Z state if the TDM Ring is not used.
control from the bytes on TXRingData. Should be connected to the
RXRingSync input of the next ZL30227 device in the Ring. This output is in
High Z state if the TDM Ring is not used.
TDM Ring port. Should be connected to the RXRingData inputs of the next
ZL30227 device in the Ring. These output are in High Z state if the TDM Ring
is not used.
TDM Ring RX Clock. Clock input signal used to align the RXRingSync and
RXRingData. Should be connected to the TXRingClk input of the previous
ZL30227 device in the Ring. There is an internal weak pull-down on this input.
TDM Ring RX Sync. Synchronization input signal used to retrieve data and
control from the bytes on RXRingData. Should be connected to the
TXRingSync output of the previous ZL30227 device in the Ring. There is an
internal weak pull-down on this input.
TDM Ring RX Data[7:0]. Data Bus connecting the RX TDM Ring port to the TX
TDM Ring port. Should be connected to the TXRingData inputs of the previous
ZL30227 device in the Ring. There are internal weak pull-downs on these
inputs.
System Clock (50 MHz nominal). In the ZL30227, this clock is used for all
internal operations of the device.
Counter Latch Clock. The clock present at this input can be divided internally
to produce the latch signal for the internal counters. Refer to the Counter
Transfer Command register for more details. This pin has an internal
pull-down.
System Reset. This is an active low input signal. It causes the device to enter
the initial state. The Clk signal must be active to reset the internal registers.
JTAG Test Clock. TCK should be pulled down if not used.
JTAG Test Mode Select. TMS is sampled on the rising edge of TCK.
JTAG Test Data Input. This pin has an internal weak pull-down.
Zarlink Semiconductor Inc.
TDM Ring Signals
ZL30226/7/8
System Signals
23
Description
Data Sheet