ZL30226/GA ZARLINK [Zarlink Semiconductor Inc], ZL30226/GA Datasheet - Page 134

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ZL30226/GA

Manufacturer Part Number
ZL30226/GA
Description
4/8/16 Port IMA/TC PHY Device for xDSL
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
AC Electrical Characteristics - System Clock and Reset
Note 1:
‡ Typical figures are at 25°C, typical supply voltages, and for design aid only: not guaranteed and not subject to production testing.
CLK period width
CLK period width LOW
CLK period width HIGH
CLK falling
RESET pulse width
CLK rising
RESET
The System Clock period cannot be longer than the TX or RX Utopia clock period.
CLK
Parameter
1
Symbol
t
t
t
t
t
CLKH
CLKR
t
CLKL
CLKF
RST
CLK
Figure 31 - System Clock and Reset
Zarlink Semiconductor Inc.
ZL30226/7/8
t
Min.
rst
8.5
8.5
19
10
t
134
clkr
Typ.
t
clkf
20
10
10
Max.
20
6
6
t
clkh
t
clk
period
Units
t
clkl
clk
ns
ns
ns
ns
ns
For full operation of
TDM Ring,
otherwise could be
longer
The min CLK period
width restrictions still
need to be
maintained
The minimum time is
measured at 1.4V
Between 10%-90%
of voltage levels
Between 10%-90%
of voltage levels
Test Conditions
Data Sheet

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