ZL30226/GA ZARLINK [Zarlink Semiconductor Inc], ZL30226/GA Datasheet - Page 130

• Manufacturer Part Number: ZL30226/GA
• Description: 4/8/16 Port IMA/TC PHY Device for xDSL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Note 1 - For internal synchronization purposes, 2 system clock cycles are required between a write access and the next valid access.
AC Electrical Characteristics - CPU Interface Intel Timing - Write Cycle
1
2
3
4
5
UP_D[15:0]
UP_A[11:0]
UP_R/W
(WRITE)
(READ)
UP_CS set-up time to UP_R/W falling
edge
Address and Data set up before
rising edge of UP_R/W
UP_AD, UP_CS and Data hold time
after UP_R/W rising edge
UP_R/W low after rising edge or
UP_CS
UP_CS high before next UP_CS low
UP_OE
UP_CS
Characteristics
t
ws
Figure 26 - CPU Interface Intel Timing - Write Access
Zarlink Semiconductor Inc.
Sym.
t
t
t
t
t
ADH
CSH
ZL30226/7/8
WS
WH
SU
ADDRESS VALID
DATA VALID
130
(see Note 1)
Min.
t
su
10
1
4
1
2
Typ.
t
adh
Max.
t
csh
t
wh
system
Units
cycle
clock
ns
ns
ns
ns
Test Conditions
Data Sheet