ZL30226/GA ZARLINK [Zarlink Semiconductor Inc], ZL30226/GA Datasheet - Page 104

• Manufacturer Part Number: ZL30226/GA
• Description: 4/8/16 Port IMA/TC PHY Device for xDSL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Hex):
15:12
Bit #
Bit #
11:8
15
14
7:4
3:0
...
1
0
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
...
R
0x0402 (1 reg)
1 register for all links.
0000
1 register per 2 TX IMA Groups. IMA Group n is paired with IMA group n+4.
For ZL30226 groups, 0, 1, 2 and 3 are used.
0C0C
0x0403 - 0x0406 (4 regs)
0: Count total Cells for Link 15.
1: Count only User Cells for Link 15.
0: Count total Cells for Link 14.
1: Count only User Cells for Link 14.
...
0: Count total Cells for Link 1.
1: Count only User Cells for Link 1.
0: Count total Cells for Link 0.
1: Count only User Cells for Link 0.
Unused. Read all 0’s.
Defines the integration period for IMA Group n+4:
1111: Reserved, do not use
1110: 2
.....
0001: 2
0000: 2
Reserved.
Defines the integration period for IMA Group n:
1111: Reserved, do not use
1110: 2
1101: 2
1100: 2
1011: 2
1010: 2
1001: 2
1000: 2
0111: 2
0110: 2
0101: 2
0100: 2
0011: 2
0010: 2
0001: 2
0000: 2
Table 81 - UTOPIA Input Cell Counter Links Register
22
22
15
Table 82 - TX IDCR Integration Registers
21
20
19
14
11
09
08
18
17
16
13
12
10
09
08
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles (preferred value for SHDSL E1 service)
clock cycles (preferred value for SHDSL T1 service)
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles
Zarlink Semiconductor Inc.
ZL30226/7/8
104
Description
Description
Data Sheet