ZL30226/GA ZARLINK [Zarlink Semiconductor Inc], ZL30226/GA Datasheet
ZL30226/GA
Related parts for ZL30226/GA
ZL30226/GA Summary of contents
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... ZL30226/7/8 Block Diagram with Built-in IMA functions Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2004, Zarlink Semiconductor Inc. All Rights Reserved. 4/8/16 Port IMA/TC PHY Device for xDSL ZL30226/GA ZL30227/GA ZL30228/GA • HEC (header error control) verification & ...
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General • Supports TDM serial links Mb/s for xDSL • Single chip ATM IMA & TC processor • Versatile TDM interface for most popular xDSL chipsets • ZL30226/7/8 devices can be spanned using a ...
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Hardware functions that are implemented in the ZL30226/7/8 device are: • Utopia Level compatible MPHY Interface • Incoming HEC verification and correction (optional) • Generation of a new HEC byte • Format outgoing cells into multi-vendor serial ...
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Device Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Link Addition ...
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AC/DC Characteristics ...
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Figure 1 - ZL30226/7/8 Block Diagram with Built-in IMA functions for IMA Groups over 4/8/16 links . . . . . 1 Figure 2 - ZL30226 Pinout (Bottom View ...
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Table 1 - IDCR Integration Register Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table 49 - Processor RX Cell Link FIFO Status Register ...
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Table 97 - IRQ IMA Group Overflow Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Pin Diagram - ZL30226 The ZL30226 uses a 384 pin PBGA with a 1.0 mm ball pitch DSTi[4] NC VDD5 TXRing- Data[ VSS ...
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Pin Diagram - ZL30227 The ZL30227 uses a 384 pin PBGA with a 1.0 mm ball pitch DSTi[4] NC VDD5 DSTi[ TXRing- Data[ VSS IC NC RXCKi ...
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Pin Diagram - ZL30228 The ZL30228 uses a 384 pin PBGA with a 1.0 mm ball pitch DSTi[4] RXCKi VDD5 DSTi[ TXRing- [3] Data[ VSS IC DSTi[3] ...
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ZL30226 Pin Description Pin # Name I/O ATM Input Port Signals (UTOPIA Transmit Interface) U2,U1,T4,T2, UTxData I UTOPIA Transmit Data Bus. 16 (or 8) bit wide data driven from ATM LAYER T1,R3,R4,R2, [15:0] device to ZL30226. Bit 15 (or 7) ...
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ZL30226 Pin Description (continued) Pin # Name I/O J3 URxClav O UTOPIA Receive Cell Available Signal. For cell-level flow control in a MPHY environment, URxClav is an active high tri-stateable signal from the ZL30226 to ATM LAYER device. L1, L2, ...
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ZL30226 Pin Description (continued) Pin # Name I/O DSTo O Serial TDM Data Output 12 and 0. Serial stream which contains transmit U25, [12] data. The output is set to high impedance for unused time slots and if ...
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ZL30226 Pin Description (continued) Pin # Name I/O AC16,AE16, RXRing I TDM Ring RX Data[7:0]. Data Bus connecting the RX TDM Ring port to the TX AF16,AC15, Data[7:0] TDM Ring port. Should be connected to the TXRingData inputs of the ...
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ZL30226 Pin Description (continued) Pin # Name I/O AB23,AC4, VSS S Ground. AC5,AC23, AD3,AD24, AE2,AE25,B2, B25,C3,C24, D4,D5,D23,E4, L11,L12,L13, L14,L15,L16, M11,M12,M13, M14,M15,M16, N11,N12,N13, N14,N15,N16, P11,P12,P13,P 14,P15,P16,R1 1,R12,R13,R1 4,R15,R16,T11 ,T12,T13, T14,T15,T16 B1,J2,M1,Y1 Not Connected. AA2,AC2,AD2, AE1,AC3,AF4, AC8,AE17, AC20,AD21, AF22,AF23, AD22,AE23, ...
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ZL30226 Pin Description (continued) Pin # Name I/O R26, T26, T24, PD I/O Pull Down. Connect to VSS via a high value resistor, e.g ohm. V23, W24,Y25, AB25, AC25, AE22, AF20, AF19, AE18, R25,T25,U26, V25,W26,W23, Y24,AA24, AB24,AD26, AC21,AD20, ...
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ZL30227 Pin Description Pin # Name I/O ATM Input Port Signals (UTOPIA Transmit Interface) U2,U1,T4,T2, UTxData I T1,R3,R4,R2, [15:0] R1,P3,P1,N1, N2,N3,M2,M4 U3 UTxPar I V1 UTxSOC I V4 UTxClk I V3 UTxEnb I V2 UTxClav O UTOPIA Transmit Cell Available ...
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ZL30227 Pin Description (continued) Pin # Name I/O K2 URxEnb I J3 URxClav O UTOPIA Receive Cell Available Signal. For cell-level flow control in a MPHY L1, URxAddr I L2, [4:0] L4, L3, K1 B7,A7,D8,C8, sr_d I/O Static Memory Data ...
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ZL30227 Pin Description (continued) Pin # Name I/O AD13 up_oe I or up_rd AE13 up_cs I AC9 up_irq O Processor Interrupt Request. Open drain signal. If this signal is low, the DSTo O Serial TDM Data Output. Serial stream which ...
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ZL30227 Pin Description (continued) Pin # Name I/O AB2,AB1 PLLREF O Output reference to an external PLL. [1:0] AA3,AA4, REFCK I AA1,Y3 [3:0] D16 TXRingClk O TDM Ring TX Clock. Clock output signal used to align the TXRingSync and A17 ...
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ZL30227 Pin Description (continued) Pin # Name I/O B5 TRST I AD1 Test1 I D19 Test2 O Test2. Must be left not connected (NC). C7 Test3 I B4 Test4 O Test4. Must be left not connected (NC). E2,H1,J1,M3, VDD5 S ...
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ZL30227 Pin Description (continued) Pin # Name I/O B1,J2,M1,Y1 AA2,AC2,AD2, AE1,AC3,AF4, AC8,AE17, AC20,AD21, AF22,AF23, AD22,AE23, AF24,AE24, AF25,AD23, AE26,R24, L23,E25,C25, B26,D24,C15, A6,A3,C4, B3,A2 P24, T23, V24,Y26, AB26, AC24, AE20,AC18 P26, M24, K24, H23, F25, C26, B23, B21 N26, L26, ...
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ZL30228 Pin Description Pin # Name I/O ATM Input Port Signals (UTOPIA Transmit Interface) U2,U1,T4,T2, UTxData I T1,R3,R4,R2, [15:0] R1,P3,P1,N1, N2,N3,M2,M4 U3 UTxPar I V1 UTxSOC I V4 UTxClk I V3 UTxEnb I V2 UTxClav O UTOPIA Transmit Cell Available ...
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ZL30228 Pin Description (continued) Pin # Name I/O J3 URxClav O UTOPIA Receive Cell Available Signal. For cell-level flow control in a MPHY L1, URxAddr I L2, [4:0] L4, L3, K1 B7,A7,D8,C8, sr_d I/O Static Memory Data Bus. Data Bus ...
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ZL30228 Pin Description (continued) Pin # Name I/O AE13 up_cs I AC9 up_irq O Processor Interrupt Request. Open drain signal. If this signal is low, the P24,R23,T23, DSTo O Serial TDM Data Output 15-0. Serial stream which contains transmit data. ...
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ZL30228 Pin Description (continued) Pin # Name I/O B17,C17,A18, TXRingData O TDM Ring TX Data[7:0]. Data Bus connecting the TX TDM Ring port to the B18,D18,C18, [7:0] A19,B19 AF13 RXRingClk I AF14 RXRingSync I AC16,AE16, RXRingData I AF16,AC15, [7:0] AE15,AF15, ...
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ZL30228 Pin Description (continued) Pin # Name I/O E2,H1,J1,M3, VDD5 S 5 Volt supply pin. Connect volt supply when interfacing to 5 volt P2,T3,Y2,AB3, AE6,AF8, AD12,AD15, AC19,AD25, AA25,V26, N25,H26,F26, A23,D20,C16, A13,A8,C5 AA23,AB04, V3.3 S 3.3 Volt supply ...
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ZL30228 Pin Description (continued) Pin # Name I/O R25,T25,U26, PD V25,W26,W23, Y24,AA24, AB24,AD26, AC21,AD20, AD19,AD18, AF18,AD16 N26,M25,L26 K26,J26,J24, H24,G23,F23, D26,D25,B24, C22,C21,A21, A20 1.0 Device Architecture The ZL30226/7/8, supported by software, implements the ATM Forum Inverse Multiplexing for Asynchronous ...
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Link State Machines The software implemented transmit and receive LSMs are independent (i.e., each link has its own LSM). LSMs rely on various events from: the ZL30226/7/8 interface, such as cell errors, excessive delay between-links, etc.; or, from the ...
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Hardware Functions The ZL30226/7/8 circuitry implements the following functions: • UTOPIA L1 and L2 compatible Interface (8-bit mode wide bus supported with UTOPIA clock MHz and 16- bit wide with UTOPIA clock ...
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The ATM Transmit Path The transmit path corresponds to a cell flow from the ATM Layer towards the PHY Layer. The ATM cell path on the transmit side starts at the UTOPIA Interface. Once ATM cells ...
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UTOPIA L2 ATM In Interface Cell In Control from IDCR Generator Filler Cell Idle Cell ICP Cell Group 0 ICP Cell Group 1 ICP Cell Group 7 Next ICP Cell Group 0 Next ICP Cell Group 1 Micro I/F Next ...
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TX Cell RAM and TX FIFO Length The internal TX Cell RAM can hold up to 128 cells. The following 10 cells are reserved for ZL30226/7/8 operation: • one ICP cell for each IMA Group for a total of ...
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ATM Transmit Path in IMA Mode The ZL30226/7/8 supports up to eight independent IMA Groups. Each of the available serial links can be assigned to any one of these IMA Groups. A serial link cannot be assigned to more ...
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In CTC mode, when using the Fixed algorithm, the Stuff event is periodic and will appear in the same IMA frame, once every 2048 cells, on each link that is part of the IMA Group. In CTC mode, when using ...
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IMA Controller (RoundRobin Scheduler) The IMA controller produces the cell stream to be sent to the TDM blocks using the following four cell types: • Data cells received from the UTOPIA port (User cells) • Filler cells • IMA ...
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Hardware controls the following bytes of the ICP cell: • Byte 5 - the HEC is always calculated and inserted by the ZL30226/7/8 • Byte 6 - the TX OAM Label is defined by the software and the value contained ...
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TX IMA Group Start-Up Initialize the TX IMA Group start-up as follows: (Note: The startup procedure below is given indicating the most important steps. A more detailed and complete sequence can be found in the Zarlink IMA Core Software). ...
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ATM In Cell_In_Control Output Controller and Cell Distribution Figure 6 - Functional Block Diagram of the Transmitter in TC Mode 2.5 ATM Transmit Path in TC Mode A maximum of sixteen independent serial interfaces can be configured in TC mode ...
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Consecutive Incorrect HEC (cell by cell) When a valid HEC is found, the CD circuit locks on the cell boundary and enters the PRESYNC state. The PRESYNC state keeps checking the HEC to ensure that the previous indication was not ...
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Cell Accepted DELTA Consecutive Correct HCS’s (PRESYNC State) Correction In normal operation, the HEC verification state machine remains in the ’correction’ state. Incoming cells containing no HEC errors are passed to the receive IMA block (RX IMA). Incoming single-bit errors ...
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RXCK S/P DSTi [0] RXCK S/P DSTi [15] TDM Ring Control To TDM Ring Figure 9 - ZL30228 Receiver Circuit in IMA Mode 3.3 ATM Receive Path in IMA Mode The block diagram in Figure 9 illustrates the ZL30228 IMA ...
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Incoming ICP cells are automatically detected by the ICP Processing block. As soon as one valid ICP cell is received, the IMA Frame State Machine moves to the IMA PRESYNC state. When Gamma-valid ICP cells are received, the state machine ...
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Loss of IMA Frame (LIF) Synchronization A link is declared out of IMA Frame (LIF) synchronization state when the IFSM goes in HUNT mode for ’gamma +2’ frames after it was in SYNC state. Loss of IMA Frame (LIF) ...
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During the start-up phase, the software can choose to collect all valid ICP cells from a RX TDM port and determine if the parameters are acceptable to proceed to start-up an IMA group. In normal IMA operating mode, the software ...
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Memory Size (Kbytes) 1024 Kb Note: Assuming a Guardband of 4 cells Table 4 - Differential Delay for Various Memory Configuration 3.3.12 Cell Sequence Recovery When an IMA Group is active, the IMA recombiner manages the pointers to the external ...
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If this slower link added, then the recombiner process has to stop for the time required to receive the cells on the ...
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Measured Delay Between Links The values and delay type for a selected link(s) or IMA Group can be read using the RX Delay Select (0x02AA) register. IMA Group delay types include: the Maximum Delay over time; the Current Maximum ...
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Write to the RX Link Control (0x00C0-0x00C7) register to select the RX options • Configure the RX serial port(s) by writing to the TDM RX Link Control (0x0700-0x070F) register • Configure the RX IMA UTOPIA port by writing to ...
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The ATM Receive Path in TC mode Up to sixteen incoming serial (typically TDM) lines can be connected to the ZL30226/7/8 receiver and forwarded to the UTOPIA L2 interface served by an external ATM-Layer device. Figure 10 illustrates four ...
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Non-Framed Mode - 2.5 Mbps In Non-framed mode, all links are able to run from 2.5 Mb/s. On the transmit side, if the TXCK is programmed as input. The transmitter will be "free running" and will ...
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This mode is selected in TDM TX Link Control (0x0600-0x060F) and TDM RX Link Control (0x0700-0x070F) by writing the following settings into those enabled links only. Data rate (bits 6: Multiplex mode (bits 4: Cell delineation ...
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RXCK 0-15 REFCK 0-3 RXCK 0-15 Figure 11 - TXCK Output Pin Source Options 4.5.1 Primary and Secondary Reference Signals Two output pins are provided to simplify the external circuitry required when using an external PLL. These two pins, PLLREF0 ...
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UTOPIA Interface Operation The ZL30226/7/8 supports the UTOPIA L1 and L2 Mode 16-bit wide bus, with odd/even parity, for cell level handshake only. In 8-bit UTOPIA mode maximum supported clock MHz and in ...
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The device will not accept a cell from the UTOPIA Interface if the internal Cell Ram is full. Status bit 0 in the General Status (0x040E) register is set indicate the ’no free cell in TX Cell ...
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UTOPIA Operation With a Single PHY A single ATM layer device with a UTOPIA L2 MPHY port can be connected to the ATM input port of one ZL30226/7/8. Another ATM-Layer device using the UTOPIA L2 MPHY input interface is ...
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Examples of UTOPIA Operation Modes Figure 12 shows the connection of one ATM Device to one ZL30228. Figure 13 shows the connection of one ATM Device with more than one ZL30228. ATM Layer ATM Figure 13 - ATM Interface ...
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ATM Layer Device Figure 14 - ATM Mixed-Mode Interface to One ZL30228 Figure 14 illustrates the implementation of a mixed mode using only 1 ZL30228. Links that are not used for IMA Groups are available in TC mode. Unused links ...
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Receive TDM I/F Counters There are four counters associated with each of the sixteen receive TDM links for a total of 64 receive counters. These counters record the following information and are active as soon as the RX TDM ...
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Note: The content of the counter for all cells in the Utopia Transmit block for the IMA Group 7 is not reset by the latch command when the counters are operating in latch mode. The counter will contain a cumulative ...
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IRQ Master Status and IRQ Master Enable Registers There is a IRQ Master Status (0x0455) register that reports interrupts generated by any event on any of the links. Each bit of this register corresponds to a link. A ’1’ ...
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Writing a ’1’ has no effect on the bits and the IRQ Link Status (0x0435-0x0444) register. Each one of these 10 interrupt sources can be enabled by writing a ’1’ in the IRQ ...
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IRQ IMA Group Overflow Status and Enable Registers The sources of IMA Group overflow conditions are organized in two levels of registers: • eight low level, 5-bit registers (one register per IMA Group) • one intermediate 4-bit register that ...
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Direct Access Direct access registers can be written or read directly by the microprocessor, without having to use other registers. Upon a write access to the ZL30226/7/8 internal registers, the data is stored in an internal latch and transferred ...
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When the new byte is different, a copy of the new byte along with the byte number is put into a dedicated preprocessor FIFO, accessible via the Processed RX Cell Link FIFO (0x0140 - 0x014F) registers. There is one preprocessor ...
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Operation of the TDM Ring is programmed via 16 Ring Tx Link (0x0181-0x0190) registers, 16 Ring Rx Link (0x01C0-0x01CF) registers and one Ring Tx Control (0x0180) register. The Ring Tx Control (0x0180) sets which ZL30226/7/8 is the master (source of ...
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Address Access Reset Value (Hex) Type 0x0052 D 000X0000000 0x0053 D 0x0080 D 000000001X0 0x0086 D 0x0087 D 0x0088 D 0x0089 D 0x008B-0x0092 D 0x0093-0x0096 D 0x009B D 0x0C0 - 0x0C7 D 0x00C8 D 0x00C9 D 0x00CA D 0x00CC - ...
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Address Access Reset Value (Hex) Type 0x0108 D 0x0140 - 0x014F D 0x0180 D 0x0181 - 0x0190 D 0x01C0 - D 0x01CF 0x0201--x0208 D 0x0209 - 0x0210 D 0x0219 - 0x021C D 0x0280 Sync 000000001X0 0x0281 D 0x0282 D 0x0283 ...
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Address Access Reset Value (Hex) Type 0x040D D 0x040E D 0x040F Sync 0x0410 - 0x041F D 0x0420 - 0x0427 D 0x0430 D 0x0431 D 0x0432 D 0x0433 D 0x0434 D 0x0435 - 0x0444 D 0x0445 - 0x0454 D 0x0455 D ...
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Detailed Register Description Address (Hex): 0x000-0x007 (8 regs) Direct access 1 register per 2 links in non-IMA mode. Link 0 is paired with link 8, link 1 with link 9 and so on. Reset Value (Hex): 0000 Bit # ...
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Address (Hex): 0x0011 (1 reg) Direct access 1 register to enable the IMA Groups.For ZL30226 groups and 3 are used. Reset Value (Bin): X000000000000000 Type 15 R Reserved. 14 R/W Reserved. Write 0 for normal operation. 13 ...
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Address (Hex): 0x0040-0x0047 (8 reg) Direct access 1 register per 2 links in non-IMA mode. Link 0 is paired with link 8, link 1 with link 9 and so on. Reset Value (Hex): 0000 Bit # Type 15:13 R Unused. ...
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Address (Hex): 0x0051 (1 reg) Direct access 1 register to enable the IMA Groups. For ZL30226 groups and 3 are used. Reset Value (Hex): 0000 Bit # Type 15:12 R Unused. Reads all 0’s. 11:8 R/W Reserved. ...
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Address (Hex): 0x0052 (1 reg) Direct access 1 register for all the UTOPIA Input ports.For ZL30226 groups and 3 are used. Reset Value (Hex): 000X000000000000 Bit # Type 1:0 R/W HEC Verification. 11: Enable HEC error correction ...
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Address (Hex): 0x0086 (1 reg) Direct access Controls the transfer of TX ICP cells. For ZL30226 groups and 3 are used. Reset Value (Hex): 00FF Bit # Type 15:8 R Unused. Read all 0’s. 7 R/W Write ...
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Address (Hex): 0x0088 (1 reg) Direct access Interrupt Enable register for the TX ICP Handler register. Reset Value (Hex): 0000 Bit # Type 15:8 R Unused. Read all 0’s. 7 R/W Write a 1 will enable the generation of an ...
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Address (Hex): 0x0093-0x0096 (4 reg) Direct access 1 register per 2 IMA groups. Group 0 is paired with Group 4, Group 1 is paired with Group 5 and so on.For ZL30226 groups are used. Reset Value ...
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Address (Hex): 0x00C0 - 0x00C7 (8 reg) Direct access 1 register per 2 links. Link 0 is paired with link 8, link 1 with link 9 and so on. Reset Value (Hex): 0C0C Bit # Type 9 R/W A value ...
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Address (Hex): 0x00C9 (1 reg) Direct access 1 register for all 16 cell delineation state machines. Reset Value (Hex): 0067 Bit # Type 15:8 R Unused, Read all 0’s. 7:4 R/W DELTA parameter value for the Cell Delineation register. The ...
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Address (Hex): 0x00D9 (1 reg) Direct access 1 register for the 16 RX links. Reset Value (Hex): 0000 Bit # Type 15 R/W An OIF state was detected on the physical link 15. Cleared by writing R/W ...
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Address (Hex): 0x00DC (1 reg) Direct access 1 register to select the link from which to extract the RX ICP cells values shown in following registers. Reset Value (Hex): 0000 Bit # Type 15:5 R Unused. Read all 0’s. 4 ...
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Address (Hex): 0x00DF (1 reg) Direct access The value is updated on completion of the write action in the RX Load Values register. Reset Value (Hex): 0000 Bit # Type 7:0 R Defines the ICP cell offset of the link ...
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Address (Hex): 0x00E3 (1 reg) Direct access The value is updated on completion of the write action in the RX Load Values register. Reset Value (Hex): 0020 Bit # Type 15:8 R Unused. Read all 0’ LIF state ...
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Address (Hex): 0x00E5 (1 reg) Direct access 1 register for all links. Reset Value (Hex): 0000 Bit # Type indicates that the IMA Frame State Machine (IFSM) for the link Synchronized State. A ...
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Address (Hex): 0x0100 (1 reg) Direct access Access for RX link Reset Value (Hex): 0000 Bit # Type 15:14 R/W These 2 bits select the type of cells stored in the RX ...
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Address (Hex): 0x0101 (1 reg) Direct access Access for RX link 15, 14, 13, 12, 11, 10 Reset Value (Hex): 0000 Bit # Type 3:2 R/W These 2 bits select the type of cells stored in the RX ...
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Address (Hex): 0x0106 (1 reg) Direct access Write to bit 3:0 of this register to select the specific link RX ICP Cell FIFO. The value is immediately updated for a read. Reset Value (Hex): 0000 Bit # Type 15:6 R ...
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Address (Hex): 0x0108 Direct access 1 register for debug. Reset Value (Hex): 0000 Bit # Type 15:6 R Unused. Always 0. 5:2 R/W Reserved. Write 0. 1 R/W 0: Compare entire cell. 1: Compare entire ICP cell. 0 R/W 0: ...
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Address (Hex): 0x0181 - 0x0190 (16 reg) Direct access 1 register per Tx Link. Reset Value (Hex): 0000 Bit # Type 15:12 R Unused. Read 0. 11 R/W ATM side: 0: Normal mode. The external RING is not connected to ...
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Address (Hex): 0x0201-0x0208 Direct access 1 register per 2 RX link. Link 0 is paired with link 8, link 1 with link 9 and so on. For ZL30226 groups and 3 are used. Reset Value (Hex): 0000 ...
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Address (Hex): 0x0219 - 0x021C (4 reg) Direct access 1 register per 2 IMA groups. IMA Group 0 is paired with IMA group 4 and so on. For ZL30226 groups and 3 are used. Reset Value (Hex): ...
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Address (Hex): 0x0280 (1 reg) Synchronized access Reset Value (Bin: 000000001X000000 Bit # Type 1:0 R/W When bit there is no access to the external RAM (no reset or read or write action done). When bit 1 ...
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Address (Hex): 0x0282 (1 reg) Direct access Used to decrement the recombiner delay for an IMA Group. The value is in the Guardband/Delta Delay register. Reset Value (Hex): 0000 Bit # Type 0 R/W Write decrement the ...
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Address (Hex): 0x0285 (1 reg) Direct access This register contains the delay value (in number of cells) selected by the RX Delay Select Register. The value always include the current guardband delay. Reset Value (Hex): 0004 Bit # Type 15:11 ...
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Address (Hex): 0x0297 (1 reg) Synchronized access Set address before the transfer is initiated with the RX External SRAM Control register. Reset Value (Hex): 0000 Bit # Type 15:4 R Unused. Read all 0’s. 3:0 R/W RX External SRAM Read/Write ...
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Address (Hex): 0x029A - 0x02A1 (8 reg) Direct access 1 register per IMA Group (value in number of cells). For ZL30226 groups and 3 are used. Reset Value (Hex): 0000 Bit # Type 15:14 R Unused. Read ...
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Address (Hex): 0x0300 - 0x0307 (8 reg) Direct access 1 register per TX IMA Group. Reset Value (Hex): 00B0 Bit # Type 15:9 R Unused. Read all 0’s. 8 R/W Reserved. Write 0 for normal operation. 7:6 R/W Value of ...
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Address (Hex): 0x0318 - 0x031F (8 reg) Direct access 1 register per 2 links, link 0 is paired with link 8, link 1 with link 9 and so on. The MSByte contains control the link 8-9 and LSByte control links ...
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Address (Hex): 0x0321 - 0x0324 (4 reg) Direct access 1 register per 2 IMA Group IMA. Group 0 is paired with IMA group 4, IMA group 1 with IMA group 5 and so on. For ZL30226 groups ...
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Address (Hex): 0x0345 (1 reg) Direct access 1 register for all links. Reset Value (Hex): 0000 Bit # Type 15 indicates a specific link (1 link per bit 15: IMA mode and started by the ...
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Address (Hex): 0x0402 (1 reg) Direct access 1 register for all links. Reset Value (Hex): 0000 Bit # Type 15 R/W 0: Count total Cells for Link 15. 1: Count only User Cells for Link 15. 14 R/W 0: Count ...
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Address (Hex): 0x040B (1 reg) Direct access 1 register for all 8 status bits. Reset Value (Hex): 0000 Bit # Type 15:8 R Unused. Read 0’s. 7:0 R/W Each bit set to ’1’ will enable the generation of the interrupt ...
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Address (Hex): 0x040F (1 reg) Synchronized access Reset Value (Hex): 0080 Bit # Type 10 R/W Counter values are latched when this bit is changed from and bit 9:8 are set to 11. Writing 0 has no ...
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Address (Hex): 0x0410 - 0x041F (16 reg) Direct access 1 register per link. The RxClk and TxClk signals must be active for correct register operation. Reset Value (Hex): 0000 Bit # Type 5 R/W This bit is set when the ...
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Address (Hex): 0x0430 (1 reg) Synchronized access The value in this register is used for internal access to the counter when the transfer command is issued. Reset Value (Hex): 0000 Bit # Type 15:8 R Unused. Read all 0’s. 7:0 ...
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Address (Hex): 0x0432 (1 reg) Synchronized access The value in this register is used for internal access to the counter when the transfer command is issued. Reset Value (Hex): 0000 Bit # Type 4:0 R/W The valid bit combinations are: ...
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Address (Hex): 0x0435 - 0x0444 (16 reg) Direct access 1 Status register per link. Reset Value (Hex): 0000 Bit # Type 15:12 R Unused. Read all 0’s. 11 R/W A ’1’ indicates the end of the LODS condition. Cleared by ...
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Address (Hex): 0x0455 (1 reg) Direct access 1 register for all 16 links. Reset Value (Hex): 0000 Bit # Type 15:0 R Each bit represents a link. A ’1’ means that the corresponding link has a valid request for interrupt. ...
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Address (Hex): 8 blocks of 32 words (16 bits) from 0x0500 to 0x05FF Direct access Access these locations directly then use transfer command to copy to internal memory. Reset Value (Hex): These registers need to be initialized for proper operation. ...
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Address (Hex): 0x0600 - 0x060F (16 reg) Direct access 1 reg. per TX link. Reset Value (Hex): 0000 Bit # Type 9 R/W Clock direction When 0, TXCK is output. When 1, TXCK is input. 8 R/W Remote Loopback When ...
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Address (Hex): 0x0630 (1 reg) Direct access 1 reg. for all 16 TXCK signals. Reset Value (Hex): 0000 Bit # Type 15 R When 1: TXCK faulty on link 15 When 1: TXCK faulty on link 14. ... ...
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Address (Hex): 0x0634- 0x0635 (2 reg) Direct access Reset Value (Hex): 0000 Bit # Type 15:5 R Unused. Read all 0’s. 4:0 R/W These 5 bits are used to select the source for the signal at PLLREF0: The valid combinations ...
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Address (Hex): 0x0700 - 0x070F (16 reg) Direct access 1 reg. per RX link. Reset Value (Hex): 0000 Bit # Type 0 R/W Reserved. Write 1 for normal operation. Table 106 - TDM RX Link Control Register (continued) Address (Hex): ...
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Address (Hex): 0x0800 - 0x0BFF, 32 Blocks of 32 words (16-bit wide) Direct access Access these locations directly, then use the transfer command to copy to internal memory. Reset Value (Hex): unknown Address Offset Type (Hex) 00 R/W Old ICP ...
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TDM Tx Link Control Register (0x600 – 0x60F) TDM Tx Mapping Registers (0x610 – 0x61F) TDM Tx Mapping Registers (0x620 – 0x62F) TDM Rx Link Control Register (0x700 – 0x70F) TDM Rx Mapping Registers (0x710 – 0x71F) TDM Rx Mapping ...
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AC/DC Characteristics Absolute Maximum Conditions* Parameter 1 Supply Voltage (2.5 volt core) Supply Voltage (3.3 volt core) Supply Voltage (5.0 volt I/O) 2 Voltage at Digital Inputs (VDD5 connected to 3.3 V) Voltage at Digital Inputs (VDD5 connected to ...
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DC Electrical Characteristics* - Voltages are with respect to ground (Vss) unless otherwise stated Characteristics Sym. 1 Supply Current Input High Voltage (Digital Inputs) 3 Input Low Voltage (Digital Inputs) 4 Input Leakage 5 Input Pin Capacitance ...
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AC Electrical Characteristics - Utopia Interface Transmit Timing (≤ 50 MHz) - Multi-PHY operation with input loads each (40 pF total). Signal name DIR UTxClk A->P UTxData[15:0], UTxSOC, A->P UTxPAR, UTxEnb, UTxAddr[4:0] UTxClav[0] A<-P ...
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AC Electrical Characteristics - Utopia Interface Transmit Timing (≤ 25 MHz) - Multi-PHY operation with input loads each (80 pF total) Signal name DIR UTxClk A->P UTxData[15:0], UTxSOC, A->P UTxPAR, UTxEnb, UTxAddr[4:0] UTxClav[0] A<-P ...
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Clock Signal Input Setup To Clock Clock Signal tT11 Signal Going Low Impedance From Clock Clock Signal t OD Note 1: The UTOPIA specification AC Characteristics are based on the timing specification for the receiver side of a signal. In ...
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AC Electrical Characteristics - External Memory Interface Timing - Read Access Item Description ZL30226/7/8 System Clock Period t Read Cycle Time RC t Address Setup Time AVRS t Address Hold Time AVRH t Chip Select Setup Time CSRS t Chip ...
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AC Electrical Characteristics - External Memory Interface Timing - Write Access Item Description t ZL30226/7/8 System Clock Period CLK t Write Cycle Time WC t Address Setup Time AVWS t Address Hold Time AVWH t Chip Select Setup Time CSWS ...
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CPU Interface Timing The CPU Interface of the ZL30226/7/8 supports both the Motorola and Intel timing modes. No Mode Select pin is required. With Motorola devices, the Motorola R/W-signal is connected to the UP_R/W pin and the UP_OE pin ...
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AC Electrical Characteristics - CPU Interface Motorola Timing - Read Cycle Characteristics 1 R/W set-up time to UP_CS falling edge 2 Data valid after UP_CS falling edge. 3 UP_AD or UP_R/W hold time after UP_CS rising edge 4 Data hold ...
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AC Electrical Characteristics - CPU Interface Intel Timing - Read Cycle Characteristics 1 R/W set-up time to UP_CS falling edge 2 Data valid after both UP_OE and UP_CS are low. 3 UP_AD or UP_R/W hold time after UP_OE rising edge ...
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AC Electrical Characteristics - CPU Interface Motorola Timing - Write Cycle Characteristics 1 UP_R/W set-up time to UP_CS falling edge 2 Address and Data set up before rising edge of UP_CS 3 UP_AD and Data hold time after UP_CS rising ...
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AC Electrical Characteristics - CPU Interface Intel Timing - Write Cycle Characteristics 1 UP_CS set-up time to UP_R/W falling edge 2 Address and Data set up before rising edge of UP_R/W 3 UP_AD, UP_CS and Data hold time after UP_R/W ...
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AC Electrical Characteristics - Serial Streams CLK Characteristic 1 CLK Period Bit rate up tp10.0 Mb/s 2 CLK Pulse Width High Bit rate up tp10.0 Mb/s 3 CLK Pulse Width Low Bit rate up tp10.0 Mb/s 4 Clock Rise/Fall Time ...
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AC Electrical Characteristics - TDM Ring Bus Characteristic 1 TXRingClk/RXRingClk period 2 TXRingClk/RXRingClk period high 3 TXRingClk/RXRingClk period low 4 TXRingSync/TXRingData output delay 5 RxRingSync/RXRingData setup time 6 RxRingSync/RxRingData hold time ‡ Typical figures are at 25°C, V =3.3 ...
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AC Electrical Characteristics - JTAG Port and RESET Pin Timing Parameter TCK period width TCK period width LOW TCK period width HIGH TDI setup time to TCK rising TDI hold time after TCK rising TMS setup time to TCK rising ...
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AC Electrical Characteristics - System Clock and Reset Parameter 1 CLK period width CLK period width LOW CLK period width HIGH CLK rising CLK falling RESET pulse width Note 1: The System Clock period cannot be longer than the TX ...
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List of Abbreviations and Acronyms AAL ATM Adaptation Layer ATM Asynchronous Transfer Mode CBR Constant Bit Rate CDV Cell Delay Variation CPE Customer Premises Equipment CRC Cyclic Redundancy Check CTC Common Transmit Clock DSU Data Service Unit FE Far ...
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QoS Quality of Service RAI Remote Alarm Indication RDI Remote Defect Indication RFI Remote Failure Indication SAR Segmentation and Reassembly SCCI Status and Control Change Indication SOC Start of Cell TC Transmission Convergence TRL Timing Reference Link TRLCR Timing Reference ...
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Cell - Fixed-size information package consisting of 53 bytes (octets) of data; of these, 5 bytes represent the cell header and 48 bytes carry the user payload and required overhead. Cell Delay Variation (CDV QoS parameter that measures ...
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Loss of Cell Delineation (LCD) - The LCD defect is reported when the OCD anomaly persists for the period of time specified in ITU-T Recommendation I.432(30)¸. The LCD defect is cleared when the OCD anomaly has not been detected for ...
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Universal Test and Operations Physical Interface for ATM (UTOPIA PHY-level interface to provide connec- tivity between ATM components. Unusable - The Unusable State is a link state indicating that a link is not in use due to a ...
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Zarlink Semiconductor 2003 All rights reserved. ISSUE ACN DATE APPRD. Package Code Previous package codes ...
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For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in ...