ZL30226/GA ZARLINK [Zarlink Semiconductor Inc], ZL30226/GA Datasheet - Page 100

• Manufacturer Part Number: ZL30226/GA
• Description: 4/8/16 Port IMA/TC PHY Device for xDSL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Hex):
Bit #
Bit #
15:8
15:9
7:0
7:6
3:0
8
5
4
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Defines the ICP cell offset of link N+8. The value of M determines which significant bits are
used as follows:
M = 256; bits 7-0 are used,
M = 128; bits 6-0 are used,
M = 64; bits 5-0 are used,
M = 32; bits 4-0 are used.
Defines the ICP cell offset of link N. The value of M determines which significant bits are
used as follows:
M = 256; bits 7-0 are used,
M = 128; bits 6-0 are used,
M = 64; bits 5-0 are used,
M = 32; bits 4-0 are used.
Unused. Read all 0’s.
Reserved. Write 0 for normal operation.
Value of M. These 2 bits specifies the value of M for the IMA Group.
00: M = 32
01: M = 64
10: M = 128
11: M = 256
Timing Mode inserted in ICP cell. A 0 means that the ITC timing mode is inserted in the
ICP cell and a 1 means that the CTC timing mode is inserted in the ICP cell.
Timing Mode in RoundRobin scheduler. A 0 means that the ITC timing mode is selected
and a 1 means that the CTC timing mode is selected for internal operation.
Reference Link. These 4 bits define which physical link is to be used as reference for
timing purposes.
0x0310 - 0x0317 (8 reg)
1 register per 2 links, used in IMA mode only. Link 0 is paired with link 8, link 1
with link 9 and so on.
physical link #
0x0300 - 0x0307 (8 reg)
1 register per TX IMA Group.
00B0
Table 72 - TX Group Control Mode Registers
Table 73 - TX ICP Cell Offset Registers
Zarlink Semiconductor Inc.
ZL30226/7/8
100
Description
Description
Data Sheet