ZL30226/GA ZARLINK [Zarlink Semiconductor Inc], ZL30226/GA Datasheet - Page 56

• Manufacturer Part Number: ZL30226/GA
• Description: 4/8/16 Port IMA/TC PHY Device for xDSL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

4.5.1
Two output pins are provided to simplify the external circuitry required when using an external PLL. These two pins,
PLLREF0 and PLLREF1, re-route any of the RXCK signals and drive the primary and secondary reference signals
of a PLL under software control. Refer to Section 8, Application Notes, for examples.
4.5.2
The ZL30226/7/8 implements circuitry to determine whether or not a selected clock signal is active. This feature is
used to ensure a clock is operational before using it as a source for one or more transmit links. A read of the TXCK
Status (0x0630), RXCK Status (0x0631) or REFCK Status (0x0632) register indicates clock activity if a bit is ’1’. A
value of ’0’ for these bits means that no transition was observed on this clock. This circuitry does not measure the
frequency of a clock signal, it only detects activity on the TXCK, RXCK and REFCK signals.
4.5.3
The clock selection circuitry selects the desired clock signal and ensures a smooth, glitch free, transition between
the current clock source and the new clock source. Clock source activity can be verified using the TXCK Status
(0x0630), RXCK Status (0x0631) or REFCK Status (0x0632) registers.
Primary and Secondary Reference Signals
Verification of Clock Activity
Clock Selection
RXCK 0-15
REFCK 0-3
RXCK 0-15
Figure 11 - TXCK Output Pin Source Options
TX Cell FIFO
Cell Delineation
Zarlink Semiconductor Inc.
ZL30226/7/8
56
P/S
S/P
PLLREF0
PLLREF1
DSTi
RXCK
DSTo
TXCK
Data Sheet