ZL30226/GA ZARLINK [Zarlink Semiconductor Inc], ZL30226/GA Datasheet - Page 15

• Manufacturer Part Number: ZL30226/GA
• Description: 4/8/16 Port IMA/TC PHY Device for xDSL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

ZL30226 Pin Description (continued)
A10,C11,D11,B
2,B12,A12,C13
11,A11,C12,D1
AE7,AD7,AC7,
AE5,AD5,AE4,
,B13,A14,B14,
AE8,AD8,AF7,
AF6,AD6,AF5,
AF3,AD4,AE3,
B7,A7,D8,C8,
C14,A15,B15
B8,D9,C9,B9
A9,C10,B10,
AE12,AC12,
AC11,AD11,
AF10,AE10,
AF11,AE11,
AD10,AF9,
AE9,AD9
A16,B16
L1, L2,
L4, L3,
AD13
Pin #
AF12
AE13
AC9
D15
AF2
K1
J3
sr_cs_1, 0
URxAddr
URxClav
up_r/w
Name
up_wr
up_oe
up_irq
sr_we
up_rd
up_cs
[18:0]
[15:0]
[11:0]
up_d
up_a
[4:0]
sr_d
[7:0]
sr_a
or
or
I/O
I/O Static Memory Data Bus. Data Bus to exchange data between the ZL30226
I/O Processor Data Bus. Data Bus to exchange data between the ZL30226 and a
O UTOPIA Receive Cell Available Signal. For cell-level flow control in a MPHY
O Static Memory Address Bus. Address bus on the external static memory.
O Static Memory Read/Not Write. If low, data is written from the ZL30226 to the
O Static Memory Chip Select Signal. Active low.
O Processor Interrupt Request. Open drain signal. If this signal is low, the
I
I
I
I
I
environment, URxClav is an active high tri-stateable signal from the ZL30226 to
ATM LAYER device.
Receive Address. Five bit wide address bus driven from the ATM to PHY
device to select the appropriate PHY address. URxAddr[4] is the MSB.
and the external static memory. sr_d[7:0] has internal weak pull-downs.
memory. If high, data is read from the memory to the ZL30226.
local processor.
Processor Address Bus. Used to select the internal registers and memory
locations of the ZL30226.
Processor Read/Not Write (Motorola Mode). This is an input signal. If low,
data is written from the processor to the ZL30226. If high, data is read from the
ZL30226 to the processor.
Processor Not Write (Intel Mode). This is an input signal, active low. If low,
data is written from the processor to the ZL30226.
Output enable (Motorola Mode). This is an input signal. This signal should be
tied to GND for Motorola timing mode.
Processor Read (Intel Mode). This is an input signal, active low. If low, data is
read from the ZL30226.
Chip Select. This is an active low input signal. If this signal is high, the ZL30226
ignores all other signals on its processor bus. If this signal is low, the ZL30226
accepts the signals on its processor bus.
ZL30226 signals to the processor that an interrupt condition is pending inside
the ZL30226.
Receiver Static Memory Interface Signals
Processor Interface Signals
Zarlink Semiconductor Inc.
ZL30226/7/8
15
Description
Data Sheet