ZL30226/GA ZARLINK [Zarlink Semiconductor Inc], ZL30226/GA Datasheet - Page 11

• Manufacturer Part Number: ZL30226/GA
• Description: 4/8/16 Port IMA/TC PHY Device for xDSL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Pin Diagram - ZL30226
The ZL30226 uses a 384 pin PBGA with a 1.0 mm ball pitch.
AA
AB
AC
AD
AE
AF
M
W
A
B
C
D
E
F
G
H
K
L
N
P
R
T
U
V
Y
J
TXCKio
RXCKi
VDD5
VDD5
VDD5
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
26
PD
PD
PD
PD
PD
26
IC
[8]
IC
[8]
DSTi[4]
DSTi[8]
RXCKi
VDD5
VDD5
VDD5
DSTo
VSS
VSS
NC
NC
NC
NC
NC
NC
[12]
NC
[12]
NC
NC
25
PD
PD
PD
PD
PD
PD
25
IC
IC
TXCKio
VSS
DSTi
VSS
NC
NC
NC
NC
NC
NC
[12]
NC
NC
NC
[12]
NC
NC
NC
NC
24
PD
PD
PD
PD
PD
24
IC
IC
IC
IC
RXCKi
VDD5
DSTo
VSS
V3.3
V3.3
V2.5
V3.3
V2.5
V3.3
VSS
VSS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
23
PD
PD
23
[4]
IC
[8]
V3.3
V3.3
NC
NC
NC
NC
22
PD
22
IC
TXCKio
DSTo
NC
NC
NC
NC
21
PD
21
IC
[4]
[4]
DSTi[0] TXRing-
RXCKi
VDD5
NC
NC
20
PD
PD
20
IC
[0]
TXRing-
Data[1]
Data[0]
VDD5
Latch
Test2 TXRing-
Clk
PD
NC
PD
19
19
Figure 2 - ZL30226 Pinout (Bottom View)
TXRing-
TXRing-
TXRing-
Data[5]
Data[4]
Data[2]
Data[3]
NC
PD
PD
PD
18
18
TXRing-
TXRing-
TXRing-
TXCKio
Data[7]
Data[6]
Sync
DSTo
V2.5
V3.3
NC
17
[0]
[0]
17
TXRing-
sr_cs_1 sr_a[1] sr_a[4]
sr_cs_0 sr_a[0] sr_a[3] sr_a[5] sr_a[8]
RXRing
RXRing
RXRing
Data[7]
Data[6]
Data[5]
VDD5
VSS
VSS
VSS
VSS
VSS
VSS
Zarlink Semiconductor Inc.
Clk
PD
16
16
ZL30226/7/8
RXRing
RXRing
RXRing
Data[4]
Data[3]
Data[2]
sr_we
VDD5 RXRing
VSS
VSS
VSS
VSS
VSS
VSS
NC
15
15
RXRing
RXRing
sr_a[2] sr_a[6]
Data[1]
Data[0]
Sync
V3.3
VSS
VSS
VSS
VSS
VSS
VSS
V2.5
14
14
11
or up_rd
RXRing
up_oe
VDD5
up_cs
V2.5
VSS
VSS
VSS
VSS
VSS
VSS
V3.3
Clk
13
13
sr_a[7]
sr_a[9]
up_r/w
up_wr
VDD5 up_a[6] up_a[3] up_a[0]
up_a
up_a
sr_a
VSS
VSS
VSS
VSS
VSS
VSS
[10]
[10]
[11]
12
12
or
up_a[7]
up_a[8] up_a[4] up_a[1]
up_a[9] up_a[5] up_a[2] VDD5
sr_a
sr_a
sr_a
sr_a
VSS
VSS
VSS
VSS
VSS
VSS
[12]
[14]
[13]
[11]
11
11
sr_a
sr_a
sr_a
V3.3
V2.5
[15]
[16]
[17]
10
10
sr_d[0] sr_d[3] sr_d[7]
sr_d[2] sr_d[5]
up_irq
sr_a
sr_d
[18]
[1]
9
9
sr_d[4]
VDD5
up_d
up_d
[14]
[15]
NC
8
8
sr_d[6]
Test3
up_d
up_d
up_d
up_d
TCK
[10]
[11]
[12]
[13]
7
7
up_d[8] up_d[5] up_d[2]
up_d[9] up_d[7]
VDD5 up_d[6] up_d[4] up_d[1]
TDO
V3.3
V3.3
TDI
NC
6
6
VDD5
TRST
TMS
VSS
VSS
5
5
Data[0]
Data[9]
UTxClk
Addr[2]
Addr[4]
REFCK
ata[10]
ata[14]
ata[13]
URxD
URxD
Reset
Test4
URxA
ddr[2]
UTxD
SOC
VSS
VSS
V3.3
URx
V2.5
UTx
V3.3
V2.5
UTx
V3.3
UTx
UTx
V3.3
VSS
NC
NC
[2]
4
4
Data[1]
Data[5]
Data[7]
Data[2]
Data[6]
UTxPar UTxD
Addr[3]
REFCK
REFCK
up_d[3] up_d[0]
ata[11]
ata[15]
ata[10]
URxD
URxD
VDD5
VDD5
VDD5
URxA
ddr[1]
UTxD
URx-
VSS
URx
URx
URx
URx
Clav
CLK
UTx
UTx
UTx
UTx
VSS
Enb
NC
NC
NC
[0]
[3]
3
3
Data Sheet
Data[0]
Data[3]
Data[8]
Data[1]
Data[3]
Addr[1]
ata[12]
ata[12]
ata[15]
REF[1]
VDD5
URxD
VDD5
VDD5
URxA
ddr[3]
UTxD
ata[8]
UTxD
VSS
URx
URx
URx
URx
URx
UTx
UTx
UTx
Clav
UTx
VSS
Par
Enb
PLL
NC
NC
NC
NC
NC
2
2
Data[2]
Data[4]
Data[6]
Data[9]
Data[4]
Data[5]
Addr[0]
REFCK
ata[13]
ata[11]
ata[14]
REF[0]
URxD
VDD5
VDD5
URxA
URxA
ddr[0]
ddr[4]
UTxD
ata[7]
UTxD
UTxD
Test1
SOC
URx
URx
URx
URx
UTx
UTx
UTx
UTx
PLL
NC
NC
NC
Clk
NC
[1]
1
1
AC
AD
AA
AB
AE
AF
W
A
B
C
D
E
F
G
H
K
M
N
P
R
T
U
V
Y
J
L