ZL30226/GA ZARLINK [Zarlink Semiconductor Inc], ZL30226/GA Datasheet - Page 109

• Manufacturer Part Number: ZL30226/GA
• Description: 4/8/16 Port IMA/TC PHY Device for xDSL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Synchronized access The value in this register is used for internal access to the counter when the
Reset Value (Hex):
Bit #
Bit #
15:0
Bit #
15:0
4:0
Type
Type
Type
R/W
R/W
R/W
When set to 1, any bit set in the IRQ Link TC Overflow Status register can generate an
interrupt. A value of 0 inhibits the generation of an interrupt. Each bit corresponds to 1 link.
Each bit represents a link. A ’1’ means that the interrupt form the corresponding link is
enabled and that the level of the IRQ pin is low if the corresponding bit in the IRQ Master
Register is set. A’0’ means that the IRQ level is not affected by the corresponding bit.
The valid bit combinations are:
10111: IMA Group 7 when UTOPIA Input counter access
10010: IMA Group 6 when UTOPIA Input counter access
...
10001: IMA Group 1 when UTOPIA Input counter access
10000: IMA Group 0 when UTOPIA Input counter access
01111: Link 15
01110: Link 14
...
00000: Link 0
Other values are not valid and should not be used.
0x0434 (1 reg)
1 register to enable interrupts from the links in TC mode. The RxClk signal must
be active for correct register operation.
00
0x0433 (1 reg)
1 register for all 16 links.
0000
0x0432 (1 reg)
transfer command is issued.
0000
Table 93 - IRQ Link TC Overflow Enable Register
Table 91 - Select Counter Register (continued)
Table 92 - IRQ Master Enable Register
Zarlink Semiconductor Inc.
ZL30226/7/8
109
Description
Description
Description
Data Sheet