RG82845M Intel, RG82845M Datasheet - Page 96

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RG82845M

Manufacturer Part Number
RG82845M
Description
Chipset Memory Controller Hub Mobile
Manufacturer
Intel
Datasheet

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Intel
3.8.17.
96
®
82845MP/82845MZ Chipset-Mobile (MCH-M)
Address Offset:
MBASE1 – Memory Base Address Register – Device #1
Default Value:
Access:
Size:
This register controls the host to AGP non-prefetchable memory accesses routing based on the following
formula:
The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of
the 32-bit address. The bottom 4 bits of this register are read-only and return zeros when read.
Configuration software must initialize this register. For the purpose of address decode, address bits
A[19:0] are assumed to be 0. Thus, the bottom of the defined memory address range will be aligned to a
1-MB boundary.
15:4
3:0
Bit
MEMORY_BASE1=< address =<MEMORY_LIMIT1
Memory Address Base 1 (MEM_BASE1). Corresponds to A[31:20] of the memory address.
Reserved
20-21h
FFF0h
Read/Write, Read Only
16 bits
Datasheet
Description
250687-002
R

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