RG82845M Intel, RG82845M Datasheet - Page 43

• Manufacturer Part Number: RG82845M
• Description: Chipset Memory Controller Hub Mobile
• Manufacturer: Intel

3.6.1.
250687-002
Note: Since there are multiple clock signals assigned to each row of a DIMM, it is important to clarify exactly
R
DRAMWIDTH—DRAM Width Register
Address Offset:
Default Value:
Access:
Size:
This register determines the width of SDRAM devices populated in each row of memory.
which row width field affects which clock signal.
7:4
Bit
3
2
1
0
Row Parameters
Reserved.
Row 3 Width. Width of devices in Row 3
0 = 16-bit wide devices, or Unpopulated (default)
1 = 8-bit wide devices
Row 2 Width. Width of devices in Row 2
0 = 16-bit wide devices, or Unpopulated (default)
1 = 8-bit wide devices
Row 1 Width. Width of devices in Row 1
0 = 16-bit wide devices, or Unpopulated (default)
1 = 8-bit wide devices
Row 0 Width. Width of devices in Row 0
0 = 16-bit wide devices, or Unpopulated (default)
1 = 8-bit wide devices
0
1
2
3
DDR Clocks Affected
SCK[2:0]/SCK[2:0]#
SCK[2:0]/SCK[2:0]#
SCK[5:3]/SCK[5:3]#
SCK[5:3]/SCK[5:3]#
2Ch
00h
R/W
8 bits
Datasheet
Descriptions
Intel
®
82845MP/82845MZ Chipset-Mobile (MCH-M)
43