RG82845M Intel, RG82845M Datasheet - Page 81

• Manufacturer Part Number: RG82845M
• Description: Chipset Memory Controller Hub Mobile
• Manufacturer: Intel

3.7.35.
250687-002
R
Address Offset:
ERRSTS – Error Status Register – Device #0
Default Value:
Access:
Size:
This register is used to report various error conditions via the hub interface messages to ICH3-M. An
SERR, SMI, or SCI error message may be generated via the hub interface A on a zero to one transition of
any of these flags when enabled in the PCICMD/ERRCMD, SMICMD, or SCICMD registers
respectively. These bits are set regardless of whether or not the SERR is enabled and generated.
15:10
8:7
Bit
9
6
5
4
3
2
1
0
Reserved
LOCK to non-DRAM Memory Flag (LCKF): When this bit is set it indicates that a host initiated
LOCK cycle targeting non-DRAM memory space occurred. Software must write a “1” to clear this
status bit.
Reserved
SERR on hub interface A Target Abort (TAHLA): When this bit is set, the MCH-M has detected that
an MCH-M originated hub interface A cycle was terminated with a Target Abort completion packet or
special cycle. Software must write a “1” to clear this bit.
MCH-M Detects Unimplemented hub interface Special Cycle (HIAUSC): When this bit is set the
MCH-M detected an Unimplemented Special Cycle on the hub interface. Software must write a “1” to
clear this bit.
AGP Access Outside of Graphics Aperture Flag (OOGF): When this bit is set it indicates that an
AGP access occurred to an address that is outside of the graphics aperture range. Software must
write a 1 to clear this status bit.
Invalid AGP Access Flag (IAAF): When this bit is set to 1 it indicates that an AGP access was
attempted outside of the graphics aperture and either to the 640k-1M range or above top of the
memory or illegal aperture access. Software must write a 1 to clear this status bit.
Invalid Graphics Aperture Translation Table Entry (ITTEF): When this bit is set to 1 it indicates
that an invalid translation table entry was returned in response to an AGP access to the graphics
aperture. Software must write a 1 to clear this bit.
Multiple-bit DRAM ECC Error Flag (DMERR): If this bit is set to 1, a memory read data transfer had
an uncorrectable multiple-bit error. When this bit is set the address and device number that caused
the error are logged in the EAP register. Software uses bits [1:0] to detect whether the logged error
address is for Single or Multiple-bit error. Once software completes the error processing, a value of ‘1’
is written to this bit field to clear the value (back to 0) and unlock the error logging mechanism.
Single-bit DRAM ECC Error Flag (DSERR): If this bit is set to 1, a memory read data transfer had a
single-bit correctable error and the corrected data was sent for the access. When this bit is set the
address, channel number, and device number that caused the error are logged in the EAP register.
Once this bit is set the EAP, CN, DN, and ES fields are locked to further single bit error updates until
the processor clears this bit by writing a 1. Software must write a “1” to clear this bit and unlock the
error logging mechanism.
C8-C9h
0000h
Read Only, Read/Write Clear
16 bits
Datasheet
Intel
®
Description
82845MP/82845MZ Chipset-Mobile (MCH-M)
81