RG82845M Intel, RG82845M Datasheet - Page 111

• Manufacturer Part Number: RG82845M
• Description: Chipset Memory Controller Hub Mobile
• Manufacturer: Intel

4.3.
4.3.1.
250687-002
Table 26. SMM Space
Note: Masters from the hub interface and AGP are not allowed to access the SMM space.
Note: High SMM: Note that this is different than in previous chipsets. In previous chipsets the High segment
R
System Management Mode (SMM) Memory Range
The MCH-M supports the use of main memory as System Management RAM (SMRAM) enabling the
use of System Management Mode. The MCH-M supports three SMRAM options: Compatible SMRAM
(C_SMRAM), High Segment (HSEG), and Top of Memory Segment (TSEG). System Management
RAM (SMRAM) space provides a memory area that is available for the SMI handler’s and code and data
storage. This memory resource is normally hidden from the system OS so that the processor has
immediate access to this memory space upon entry to SMM. MCH-M provides three SMRAM options:
SMM Space Definition
The addressed SMM space and the DRAM SMM space define SMM space. The addressed SMM space
is defined as the range of bus addresses used by the processor to access SMM space. DRAM SMM space
is defined as the range of physical DRAM memory locations containing the SMM code. SMM space can
be accessed at one of three transaction address ranges: Compatible, High and TSEG. The Compatible
and TSEG SMM space is not remapped and therefore the addressed and DRAM SMM space is the same
address range. Since the High SMM space is remapped the addressed and DRAM SMM space is a
different address range. Note that the High DRAM space is the same as the Compatible Transaction
Address space. Therefore the table below describes three unique address ranges:
These abbreviations are used later in the table describing SMM Space Transaction Handling.
was the 384-KB region from A0000h to FFFFFh. However, C0000h to FFFFFh was not practically
useful so it is deleted in MCH-M.
TSEG SMM: Note that this is different than in previous chip sets. In previous chip sets the TSEG
address space was offset by 256 MB to allow for simpler decoding and the TSEG was remapped to just
under the TOM. In the MCH-M 256 MB do not offset the TSEG region and it is not remapped.
SMM Space Enabled
Compatible©
High (H)
TSEG (T)
• Below 1 MByte option that supports compatible SMI handlers.
• Above 1 MByte option that allows new SMI handlers to execute with write-back cacheable
• Optional larger write-back cacheable T_SEG area from 128 KB to 1MB in size above 1 MByte that
• Compatible Transaction Address (Adr C)
• High Transaction Address (Adr H)
• TSEG Transaction Address (Adr T)
SMRAM.
is reserved from the highest area in system DRAM memory. The above 1 MByte solutions require
changes to compatible SMRAM handlers’ code to properly execute above 1 MByte.
Transaction Address Space (Adr)
A0000h to BFFFFh
0FEDA0000h to 0FEDBFFFFh
(TOM-TSEG_SZ) to TOM
Datasheet
Intel
®
82845MP/82845MZ Chipset-Mobile (MCH-M)
DRAM Space (DRAM)
A0000h to BFFFFh
A0000h to BFFFFh
(TOM-TSEG_SZ) to TOM
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