RG82845M Intel, RG82845M Datasheet - Page 94

• Manufacturer Part Number: RG82845M
• Description: Chipset Memory Controller Hub Mobile
• Manufacturer: Intel

Intel
3.8.14.
3.8.15.
94
®
82845MP/82845MZ Chipset-Mobile (MCH-M)
Address Offset:
Address Offset:
IOBASE1 – I/O Base Address Register – Device #1
Default Value:
Access:
Size:
This register controls the hosts to AGP I/O access routing based on the following formula:
Only the upper 4 bits are programmable. For the purpose of address decode address bits A[11:0] are
treated as 0. Thus the bottom of the defined I/O address range will be aligned to a 4-KB boundary.
IOLIMIT1 – I/O Limit Address Register – Device #1
Default Value:
Access:
Size:
This register controls the hosts to AGP I/O access routing based on the following formula:
Only the upper 4 bits are programmable. For the purpose of address decode address bits A[11:0] are
assumed to be FFFh. Thus, the top of the defined I/O address range will be at the top of a 4-KB aligned
address block.
7:4
3:0
7:4
3:0
Bit
Bit
IO_BASE=< address =<IO_LIMIT
IO_BASE=< address =<IO_LIMIT
I/O Address Base. Corresponds to A[15:12] of the I/O address. Default=Fh
Reserved
I/O Address Limit. Corresponds to A[15:12] of the I/O address. Default=0h
Reserved (Only 16-bit addressing supported)
1Ch
F0h
Read/Write, Read Only
8 bits
1Dh
00h
Read/Write, Read Only
8 bits
Datasheet
Description
Description
250687-002
R