RG82845M Intel, RG82845M Datasheet - Page 13

• Manufacturer Part Number: RG82845M
• Description: Chipset Memory Controller Hub Mobile
• Manufacturer: Intel

250687-002
Intel
R
Processor/Host Bus Support
Memory System
System Interrupts
 Supports the Mobile Intel Pentium 4 Processor-M
 Supports the Intel Pentium
 2x Address, 4x Data
 Mobile Intel Pentium 4 Processor-M System Bus
 Supports system bus at 400 MT/s (100 MHz)
 Supports host bus Dynamic Bus Inversion (DBI)
 Supports 32-bit host bus addressing
 12 deep In-Order Queue
 AGTL+ bus driver technology with integrated
 Directly supports one DDR channel, 64b wide (72b
 Supports 200 and 266-MHz DDR compliant
 Supports 64-Mb, 128-Mb, 256-Mb and 512-Mb
 All supported devices have 4 banks
 Configurable optional ECC operation (single bit
 Supports up to 16 simultaneous open pages
 Supports page sizes of 2 KB, 4 KB, 8 KB, and 16
 Thermal throttling scheme to selectively throttle
 Max of 2 double-sided (4 rows populated) with
 Largest memory supported is 1 GB (845MZ
 Supports only System Bus interrupt delivery
 Supports interrupts signaled as upstream Memory
 MSI direct to the System Bus
 Supports peer MSI between hub interface and AGP
 Provides redirection for IPI and upstream
CPU
the Enhanced Mode Scaleable Bus Protocol
interrupt delivery
AGTL termination resistors
with ECC).
devices (845MZ supports 200 MHz DDR only)
technologies for x16 devices and x8 devices.
Error Correction and multiple bit Error Detection)
KB. Page size is individually selected for every
row.
reads and/or writes. Throttling can be triggered by
preset read/write bandwidth limits.
unbuffered PC2100 DDR (with or without ECC)
SO-DIMMs (845MZ supports only 200-MHz
DDR).
supports only up to 512 MB).
mechanism
Writes from AGP/PCI (PCI semantics only) and
hub interface
interrupts to the System Bus
®
845 Chipset MCH-M Features

4 processor subset of
Datasheet
Intel
Accelerated Graphics Port (AGP) Interface
Hub Interface to ICH3-M
Power Management
Package
®
 Supports a single AGP device (either a connector
 AGP Support
 Supports AGP 2.0 including 1x, 2x, and 4x AGP
 Supports only 1.5-V AGP electricals
 32 deep AGP request queue
 PCI semantic (FRAME# initiated) accesses to
 High priority access support
 Hierarchical PCI configuration mechanism
 Delayed transaction support for AGP-to-DRAM
 32-bit upstream address support for inbound AGP
 32-bit downstream address support for outbound
 AGP Busy/Stop Protocol
 AGP Clamping and Sense Amp Control
 266-MB/s, point-to-point hub interface to ICH3-M
 66-MHz base clock
 Supports the following traffic types to the ICH3-M
 SMRAM space remapping to A0000h (128 KB)
 Supports extended SMRAM space above 256 MB,
 APM Rev 1.2 compliant power management
 Suspend to System Memory
 ACPI 2.0 Support
 Intel SpeedStep technology support
 Cache coherency with CPU in sleep mode
 Dynamic Memory Power-down
 Package options
 593-pin FC-BGA (37.5 x 37.5 mm)
82845MP/82845MZ Chipset-Mobile (MCH-M)
 Hub interface-to-AGP memory writes
 Hub interface-to-DRAM
 CPU-to-hub interface
 Messaging
or on the motherboard)
data transfers and 2x/4x Fast Write protocol
DRAM are snooped
FRAME# semantic reads that can not be serviced
immediately
and PCI cycles
PCI and Fast Write cycles
additional 128K/256K/512K TSEG from Top of
Memory, cacheable (cacheability controlled by
CPU)
 MSI Interrupt messages
 Power Management state change
 SMI, SCI and SERR error indication
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