RG82845M Intel, RG82845M Datasheet - Page 60

• Manufacturer Part Number: RG82845M
• Description: Chipset Memory Controller Hub Mobile
• Manufacturer: Intel

Intel
3.7.17.
60
®
82845MP/82845MZ Chipset-Mobile (MCH-M)
Offset:
DRT – DRAM Timing Register – Device #0
Default:
Access:
Size:
31:19
18:16
15:11
10:9
8:6
5:4
Bit
3
2
1
0
00:
01:
10:
11:
Reserved
Reserved
Reserved
Reserved
Reserved
DRAM Idle Timer: This field determines the number of clocks the DRAM controller will remain in the
idle state before it begins precharging all pages.
000
001 0
010 8 DRAM clocks
011 16 DRAM clocks
100 64 DRAM clocks
Others: reserved
Activate to Precharge delay (tRAS). This bit controls the number of DRAM clocks for tRAS.
00 7 Clocks
01 6 Clocks
10 5 Clocks
11 Reserved
CAS# Latency (tCL). This bit controls the number of DRAM Clocks between when a read command
is sampled by the SDRAMs and when the MCH-M samples read data from the SDRAMs.
DRAM RAS# to CAS# Delay (tRCD). This bit controls the number of clocks inserted between a row
activate command and a read or write command to that row.
Encoding
0:
1:
DRAM RAS# Precharge (tRP). This bit controls the number of clocks that are inserted between a
row precharge command and an activate command to the same row.
Encoding
0:
1:
Infinite
3 DRAM Clocks (Default)
2 DRAM Clocks
3 DRAM Clocks(Default)
2 DRAM Clocks
tRCD
tRP
2.5
2 Clocks
Reserved
Reserved
78-7Bh
00000010h
Read/Write
32 bits
Datasheet
Description
250687-002
R